Synopsys Aerospace and Defense Verification Seminar

Please join us for a free Aerospace and Defense Verification Seminar.

The overall complexity and size of FPGA designs has grown significantly, driving the need for very high quality verification over the past several years. A device failure can result in loss of information, property or worse, life.

Security checking, DO-254 design assurance, superior performance of Verilog and VHDL, UVM methodologies, MATLAB integration, static and formal verification solutions, verification intent specification and traceability, advanced debug capabilities, total coverage models, fault injection capabilities and Triple Modular Redundancy (TMR) for error detection and mitigation for FPGA design flows are methods that have become a requirement in today’s FPGA Aerospace and Defense products.


9:30       Registration and Breakfast
10:00     Overview - Synopsys Solutions Driving Growth in Aerospace and Defense Markets
10:45     Innovation in Simulation and Debug to accelerate design verification
11:45     Break
12:00     Supplement DO-254 Compliance methodologies using Lint/CDC Checks
12:30     Accelerate Coverage Closure utilizing Formal Verification
13:00     Design with Confidence – Leverage advanced High Reliability and Safety Critical design techniques
13:30     Coverage-Driven Execution Management for Faster Verification Closure
14:00     Wrap-up and Lunch

If you are a verification engineer, design engineer, system architect, program manager or design manager focusing on FPGA for Aerospace and Defense applications, you won’t want to miss this event. 

Register today for the seminar.

If you wish to invite additional members of your team, please forward this mail.

Lunch is included


Tuesday, 20th November
Dan Accadia, 122 Ramot Yam St. Herzliya Beach, Herzliya, 46851