Synopsys, Inc. (Nasdaq:SNPS) today announced the new HAPS®-80 FPGA-Based Prototyping Systems, a part of Synopsys' end-to-end Prototyping Solution. The HAPS-80 systems deliver up to 100 MHz multi-FPGA performance and new proprietary high-speed time-domain multiplexing (HSTDM) technology. HAPS-80 with ProtoCompiler design automation and debug software uses the latest Xilinx Virtex UltraScale VU440 devices with 26-million-ASIC-gates capacity per FPGA, supporting designs up to 1.6 billion ASIC gates. The combination of HAPS hardware and ProtoCompiler software significantly accelerates software development, hardware/software integration and system validation.
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ProtoCompiler software, which has built-in knowledge of the HAPS system architecture automates partitioning and enables an average time to first prototype of less than two weeks and subsequent compile iterations in hours compared to non-integrated prototypes. ProtoCompiler takes advantage of HAPS-80’s new HSTDM capabilities to automatically select the optimum mix of pin-multiplexing schemes to best match the design under test. The integrated HAPS-80 solution delivers performance of up to 300 MHz for single FPGA designs, up to 100 MHz for multi-FPGA without pin-multiplexing and up to 30 MHz for multi-FPGA with new proprietary high-speed pin-multiplexing. The increased system performance of the HAPS-80 systems enables OS booting to the command prompt in less than a minute, allowing designers to probe and initialize device hardware such as CPU, timers and UARTs. HAPS-80 also enables at-speed operation of real world I/O.
“Synopsys has used six prior generations of Xilinx FPGA devices and is a long-term business partner of Xilinx for FPGA-based prototyping. Synopsys’ tightly integrated hardware and software HAPS FPGA-based prototyping solution is positioned to deliver the highest performance and capability from the Virtex® UltraScale™ VU440 device,” said Hanneke Krekels, director of test, measurement and emulation market business at Xilinx. “UltraScale devices deliver a 2.2x increase in device density and 21 percent more I/O, which are ideally suited for the multi-FPGA partitioning of complex SoCs prototyped with HAPS systems.”
ProtoCompiler’s automated RTL-to-FPGA image timing-driven flow delivers the highest prototype performance and quickest turnaround times compared to the previous generation. ProtoCompiler enables the creation of prototypes with an optimum multi-FPGA design partition, lowest pin multiplexing ratios, optimized synthesis and guided FPGA place and route. These features enable designers to easily utilize the entire capacity range of HAPS-80, which supports up to 1.6 billion ASIC gates. ProtoCompiler’s hierarchical IP-to-SoC flow encapsulates RTL, design prototyping constraints, pre-defined debug visibility access points and synthesis directives, eliminating the need to replicate these tasks in an SoC and reducing the integration time by weeks.
“Baikal-T1, the world's first silicon implementation of the Imagination MIPS Warrior P5600 CPU, is the result of our commitment to innovation and high quality that our R&D center bases on rigorous hardware/software integration and system validation methods. We rely on Synopsys HAPS prototyping systems to deliver high-performance ASIC prototypes, like the one for Baikal-T1, on a rapid delivery schedule,” said Gregory Khrenov, CTO at Baikal Electronics. “We expect the features of HAPS-80 will benefit our future engineering projects.”
HAPS-80 systems deliver superior debug visibility and automation through always available HAPS Deep Trace Debug Gen4 (DTD4) technology, providing the ability to capture more than 1000 debug signal bits per FPGA at speed. Debug data acquisition, debug storage memory and dedicated debug routes are built into the HAPS-80 systems and automatically inserted by ProtoCompiler to ensure minimally invasive debug is always available to the user. HAPS DTD4, in combination with Synopsys Verdi® debug software, helps designers rapidly visualize complex design behavior in the context of the original RTL source for a simulator-like experience, reducing debug time by up to 50 percent. In addition, the integration of HAPS and ProtoCompiler with the Verification Continuum’s Unified Compile technology eases migration between Synopsys VCS® simulation, ZeBu® emulation and HAPS prototyping to save up to months of design and verification time.
The HAPS Universal Multi-Resource Bus (UMRBus) host connectivity enables hybrid prototyping, global accessibility and prototyping farm use modes. The UMRBus provides seamless connection between HAPS-80 systems and Synopsys’ Virtualizer-based virtual prototypes to create an integrated hybrid prototyping environment for early software development and hardware/software integration. In addition, HAPS-80 is backward compatible with HAPS-70, enabling designers to reuse existing systems and hardware accessories. The native Ethernet connection in the HAPS-80 system enables global system accessibility via connection to a standard Ethernet. The HAPS-80 solution supports multi-design mode to execute multiple designs simultaneously across HAPS systems in an enterprise configuration, delivering the highest prototype utilization and a greater return on investment for multiple project usage.
“We have optimized every generation of our HAPS prototyping systems to deliver the highest system performance and designer productivity. The new HAPS-80 series addresses SoC designers’ pain points in the areas of performance, scalability, time to first prototype and debug, while maintaining interoperability with HAPS-70 systems,” said John Koeter, vice president of marketing for IP and prototyping at Synopsys. “The unique combination of HAPS hardware and ProtoCompiler software delivers the fastest time to first prototype with the highest performance to accelerate software development, hardware/software integration and system validation of large SoC and GPU designs.”