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Synopsys is introducing two new products that uniquely address the challenges of testing SoCs:
As SoCs increase in size and complexity, higher compression levels are required to maintain low test costs and achieve higher test quality, even as fewer pins are being allocated for test. DFTMAX Ultra addresses these challenges with new technology that is built into Synopsys' Design Compiler RTL synthesis:
Full Story: Synopsys Announces DFTMAX Ultra to Significantly Reduce Silicon Test Costs
Overview Video: Introducing DFTMAX Ultra
Increasing complexity also makes it essential to use analog/mixed-signal IP, digital logic cores, memory and interface IP. The DesignWare STAR Hierarchical System offers a hierarchical approach for rapidly implementing test for the entire SoC to meet cost, quality and schedule goals.