The new ARC HS Processor Family utilizes the next-generation ARCv2 instruction-set architecture (ISA), which enables the implementation of high performance embedded and deeply embedded designs with ultra-low power consumption and a very compact silicon footprint. When implemented in typical 28-nm processes, the HS cores consume as little as 0.025mW/MHz in an area as small as 0.15mm2. The cores feature a high-speed 10-stage pipeline that supports out-of-order execution, minimizing idle processor cycles and maximizing instruction throughput. Sophisticated branch prediction and a late-stage ALU improve the efficiency of instruction processing. To speed the execution of math functions, the ARC HS Processors give designers the option to implement a hardware integer divider, instructions for 64-bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a configurable IEEE 754-compliant floating point unit (single- or double-precision or both). The ARCv2-based cores provide an 18 percent improvement in code density compared to previous generation ARC cores, reducing memory requirements. HS processors also support close coupled memory as well as instruction and data cache (HS36 only), with new 64-bit load-double/store-double and unaligned memory access capabilities that accelerate data transfers. Optional error-correcting code (ECC) hardware is available for all memories in the processor for applications that require a higher level of memory reliability and protection.
"Designing processors for high performance is simple when power and transistor budgets are not a concern. Much more difficult is designing small, efficient processors that offer enough performance for today plus additional headroom for future growth," said Linley Gwennap, principal analyst of The Linley Group. "To optimize their ARC HS cores for embedded applications, Synopsys took a more streamlined approach, using fewer transistors and less power yet still delivering high throughput with an unusually flexible CPU that SoC designers can customize extensively. Its strong power efficiency and low-cost silicon footprint will appeal to many embedded-system developers."