Synopsys DesignWare STAR Memory System Stands the Test of Time
In the fast-moving semiconductor test market, 11 years is a long time to be on top. Many new products are quickly replaced and just as quickly forgotten. Most products never win awards, and the few that do, rarely win more than one
Synopsys' DesignWare® STAR Memory System® is one of those rare test products. For the second time it has received a Test & Measurement World Best in Test Award. This year it was honored with the “Test of Time” award which recognizes a test, measurement, or inspection product that continues to provide state-of-the-art service for more than five years after its introduction. In 2002 it received the Best in Test “Product of the Year” award. These awards truly represent the industry’s appraisal of a product. The Test & Measurement World's editorial staff selects finalists and the audience casts votes for the products they feel feature the year’s most significant innovations. Best in Test and Test of Time winners are determined by a combination of audience votes and balloting by the editorial staff.
Advanced test algorithms providing coverage for memory defects at 20-nm nodes and below, and the solution’s performance- and area-optimized architecture were highlighted by readers and the editors as the primary motivation for selecting DesignWare STAR Memory System for Test & Measurement World’s Test of Time award.
First introduced in 2001 as a comprehensive integrated test, repair and diagnostic solution for Synopsys DesignWare Embedded Memories, the STAR Memory System has extended its capabilities to support memories from all vendors and has shipped in over a billion chips with memories in 180-nm planar down to 14-nm FinFET processes.
The STAR Memory System offers:
Optimized memory test and repair algorithms that efficiently address new memory defects, including process variation faults and resistive faults, at 20 nanometers (nm) and below
New hierarchical architecture that delivers up to a 30 percent reduction in memory test and repair area
Hierarchical implementation that accelerates design cycles by allowing incremental generation, integration, and verification of test and repair IP at various design hierarchy levels
Support for test interfaces of high-performance processor cores, enabling designers to maximize productivity and system-on-chip (SoC) performance
Protection against soft errors with multi-bit upset error correcting codes (ECC)
Advanced failure diagnosis with physical failed bitmaps and XY coordinates of failing bit cells
The DesignWare STAR Memory System team proudly showcase the 2013 Best in Test award
Mher Mkhoyan (left), Sandeep Kaushik, Yervant Zorian, Karen Darbinyan and Arun Kumar.