Synopsys Continues Performance Leadership with Latest Release of FastSPICE Solutions

The complex nature of nanometer circuits, FinFET 3D structure and the increased complexity of the power network in today’s advanced low-power SoCs require designers to simulate more PVT corners with more post-layout parasitic effects than ever before. The 2013.12 release of Synopsys’ FastSPICE solutions, CustomSim and FineSim Pro, deliver faster simulation speed and a host of significant innovations targeted for applications in advanced FinFET as well as established process node designs.

CustomSim 2013.12 delivers faster speed for advanced node SRAM post-layout simulation, while maintaining the same expected accuracy.

Fundamentals and circuit reliability analysis

  • 3X speed-up for SRAM designs
  • 2X DC simulation speed-up
  • New capabilities in circuit reliability simulation
  • Multi-technology post-layout simulation

CustomSim’s speed-up is achieved as a result of several core innovations in transient and DC simulation algorithms that are targeted for circuits such as SRAM.

The enhanced CustomSim electromigration and IR Drop (EMIR) circuit reliability simulation, certified by TSMC for the 16-nanometer process node, offers a high-performance EMIR solution for custom IP blocks.

To address the growing need for simulating circuits built with digital and analog blocks at different process nodes, CustomSim now supports multi-technology post-layout simulation.

Mixed-signal verification

  • UPF support for low-power mixed-signal verification
  • Support for SystemVerilog-based methodology with AMS Testbench support
  • Save and Restore capability for significant productivity gain

CustomSim and VCS, the industry-leading solution for fast mixed-signal SoC verification, now supports a SystemVerilog-based methodology with AMS Testbench and enhanced UPF-based low-power verification. With the solution’s proven performance and transistor-level simulation accuracy, the new capabilities enable customers to perform mixed-signal regression testing and improve mixed-signal verification coverage. The new Save and Restore feature delivers additional productivity for mixed-signal verification.

FineSim 2013.12 delivers faster speed and improved multi CPU simulation scalability for FineSim Pro.

Fundamentals and circuit reliability analysis

  • 2X speed-up for SRAM post-layout timing simulations
  • 3X faster on 8 CPUs
  • MOS device aging analysis

The FineSim 2013.12 speed-up is achieved by enhancing core engine, RC reduction and power network simulation algorithms. Multicore simulation scaling capability has been extended from 4 to 8 CPUs to achieve up to 3X faster throughput. FineSim’s reliability analysis has added supports for MOS device aging, a proven capability that is already incorporated in HSPICE and CustomSim. “As circuit designers are continually pushing the technology envelope, building bigger and more complex SoCs, they look for their EDA partners to help address challenges in circuit verification,” said Farhad Hayat, senior director of marketing at Synopsys. “The latest releases of CustomSim and FineSim extend our performance and functionality leadership, providing our customers with best-in-class technology to make design teams more productive and more easily achieve time-to-market goals.”

Customers can download CustomSim and FineSim versions 2013.12 from the Synopsys website using their SolvNet accounts or contact their Synopsys sales or applications consultant representatives to download the new versions.

Learn more about Synopsys’ FastSPICE solutions