SNUG Silicon Valley: Test, Simulation, Flip Chip Implementation, UPF and UVM Papers Win Top Awards

Insightful Keynotes and High Attendance among Highlights of SNUG Silicon Valley 2012

Featuring 51 tutorials, 38 user papers, three keynotes and numerous networking opportunities, the SNUG Silicon Valley 2012 program was packed with high-quality technical content. Speakers from companies addressing some of today’s toughest engineering challenges presented the most effective solutions for tackling digital and analog ICs, IP, FPGAs, systems design and more. Day three featured the second-annual IP Summit, drawing significant interest from attendees. This year’s high attendance reflects the increasing value of this industry event: nearly 2400 designers attended to learn from each other and from other technology leaders.

“SNUG has always been my favorite industry conference, and this year’s was the best ever,” said John Busco, SNUG Technical Chair and ASIC Design Manager at NVIDIA. “We had users from a broad assortment of companies presenting interesting leading-edge work in verification, implementation, test, low power, and other areas. The program was complemented by practical tutorials and thought-provoking keynotes and vision sessions. Attendance was high, yet the logistics flowed smoothly. Attendees embraced first-time innovations such as electronic surveys to make this the ‘greenest’ SNUG, as well. Congratulations and thanks to all the presenters, technical committee members and attendees who make this the best users group in the industry.”

As in previous years, attendees chose their favorite three papers and Best First-Time Presenter winners. The SNUG Technical Committee also gave awards for papers that demonstrated innovation and addressed top design challenges.

Milind Sonawane, Jonathon E. Colburn and Amit Sanghani of NVIDIA won both the Best Paper Award and Best First-Time Presenter Award for their paper, “Optimizing Test Times using a Scan Deserializer/Serializer Architecture.”

The “X-Propagation: An Alternative to Gate-Level Simulation” paper won the second place Best Paper Award and received an Honorable Mention Award from the Technical Committee.

The third place Best Paper Award went to Prasanth Koduri, Sampath Oks, Anupam Gangopadhyay and Santhosh Pillai of Samsung, and Susheel Sharma of Synopsys, Inc. for their paper, “Developing and Implementing a Flip Chip Interface using IC Compiler.”

The Technical Committee Award went to Jatin Mistry of the University of Southampton and James Myers of ARM Ltd. for their paper, “An ARM Cortex-M0 for Energy Harvesting Systems: A Novel Application of UPF with Synopsys’ Galaxy Platform.”

The Technical Committee also recognized Ravi Ram, Warren Anderson and Shyam Sivakumar of Advanced Micro Devices, Inc. and Vijay Akkaraju of Synopsys, Inc. with an Honorable Mention Award for their paper, “Universal Verification Methodology (UVM)-Based Random Verification through VCS and CustomSim in Analog Mixed-Signal Designs for Faster Coverage Closure.”

Keynotes at this year’s SNUG Silicon Valley featured Synopsys Chairman and CEO Aart de Geus, ARM Executive Vice President John Cornish, and Dr. Chenming Hu, Professor Emeritus of the University of California, Berkeley and former TSMC CTO.

Dr. de Geus opened the conference by describing new strategies and methodologies semiconductor players will need to achieve the critical mass necessary to craft productive and creative solutions within a design ecosystem that is more complex than anything seen yet in our history. His overview of recent technology advancements from Synopsys included the company’s 20-nanometer (nm) implementation solution, 3D-IC, Yield Explorer Snapshot, SystemVerilog VIP, Protocol Analyzer, the VDK Family for ARM Cortex Processors, and the DesignWare® SoundWave Audio Subsystem.

In reference to the recent completion of Synopsys’ acquisition of Magma Design Automation, Dr. de Geus reiterated that the combination of the two companies’ will enable Synopsys to more rapidly meet the needs of leading-edge semiconductor designers for ever more sophisticated design tools. He also extended a warm welcome to the Magma users in attendance at SNUG.

Mr. Cornish kicked off day two with a broad perspective on low-power design. He emphasized the importance of optimizing all aspects of system design for power, and the need for system profiling and analysis as well as for defining new industry standards. He also highlighted the ARM big.LITTLE processor strategy for high-performance and low-power compute requirements.

The keynotes from Dr. de Geus and Mr. Cornish are broadly available for replay from the SNUG community site on

On day three, Professor Hu discussed the invention of FinFETs. He explained the factors that have rendered MOSFETs obsolete at geometries below 20 nm and presented the advancements which have made modern FinFETs possible in bulk CMOS. Dr. Hu acknowledged that Synopsys’ TCAD technology was used in the design of these FinFETs and thanked Synopsys for their support in developing the newest BSIM standard for simulation of FinFETs in HSPICE.

Day three also featured the second annual IP Summit at SNUG. The nine sessions were tailored to help users understand and address the challenges, as well as reap the benefits, of integrating IP into SoC designs.

Two evening events rounded out the SNUG program. On Monday night, Synopsys and 65 partners hosted the Designer Community Expo where 500 users networked with colleagues while enjoying a wide variety of appetizers, drinks and fantastic prize drawings. Tuesday night was transformed into Silicon Valley’s biggest watering hole, SNUG Pub, which provided an opportunity for more than 600 attendees to converse over a drink; play air hockey, darts or other games; and enjoy international pub snacks in a relaxed setting.

For 22 years, SNUG has offered attendees an excellent technical program plus an opportunity to connect with Synopsys executives, design ecosystem partners and the local design engineering community. For more information on future SNUG conferences, visit