SNUG San Jose 2011 Recognizes Technical Excellence, Breaks Records

SNUG® San Jose 2011 reached a new milestone in the user group's 21-year history: It was the largest EDA user's group ever, with 2,375 customer users engaging on a wide range of technical challenges and solutions at the Santa Clara Convention Center.

As one user said, "It's good to come to SNUG and connect with other companies to get other perspectives on the challenges we're sharing…and the challenges that are unique to us."

SNUG Technical Chair John Busco shares the enthusiasm of users at the conference. "SNUG San Jose received very good feedback from users who attended this year. We are able to draw record attendance because SNUG is all about designers and the real challenges we face," Mr. Busco said. "Excellent user papers, panels and presentations are at the core of the conference and cover a wide variety of chip design disciplines. Users also look forward to the opportunity to hear electronics industry leaders share their vision of what’s happening and how it will affect chip design and EDA."

Each year, SNUG highlights the technical excellence of its participants by presenting awards to the best papers and presenters, as chosen by conference attendees. This year's sessions included in-depth presentations and analyses of a range of technology topics, including IC design and verification, cloud computing, FPGAs, compute and design infrastructure, system-level design, IP and more. SNUG San Jose 2011 also featured our first-ever IP Summit, where topics covered MIPI, USB 3.0, ARC processors, logic libraries and memories.

SNUG attendees awarded first place for best paper to Phil Simpson and Jennifer Stephenson of Altera Corp. for their paper, "A Methodology for Creating Reusable Design Blocks Targeting FPGA Devices."

Second place was awarded to Richard Bishop of Advanced Micro Devices, Inc. for his paper, "A Case for Adopting Galaxy Constraint Analyzer." Mr. Bishop also received a Technical Committee Honorable Mention.

Third place was awarded to Bob Turner of Broadcom Corporation and Nish Balaji of Synopsys for their paper, "Implementing a High-Speed, Low-Power ARM Cortex A9 falcon_cpu using Synopsys Physical Guidance."

The award for best first-time presenter went to Gary Gibson of Cray Inc. for his paper, "Implementing JTAG using the CHIPit UMRBus."

The Technical Committee Award went to Alexander Tetelbaum and Rich Laubhan of LSI Corp., and David Keyser of Synopsys for their joint paper titled, "Advanced OCV Timing Derating Experience."

A Technical Committee Honorable Mention was also awarded to Martin Amodeo and Dwight Elvey of Advanced Micro Devices, Inc., and Aurelia De Colle and Tim Ayres of Synopsys for their paper, "AMD Latch-based Design Methodologies with TetraMAX ATPG."

Keynotes at this year's SNUG San Jose featured Synopsys Chairman and CEO Aart de Geus, Synopsys low power guru Godwin Maben, and Samsung Electronics Executive Vice President Kwang-Hyun Kim.

Dr. de Geus opened the conference by describing the semiconductor race as being on "fast forward" as designers focus on creating "smart everything." During his keynote, Aart shared Synopsys' 'cloud' strategy and also announced DC Explorer, Synopsys' new RTL exploration solution. DC Explorer enables designers to quickly and efficiently perform what/if analyses of various design configurations, even before the design data is complete, in order to create a better starting point for Design Compiler RTL synthesis and accelerate design schedules.

In his keynote on day two, Mr. Maben described multiple ways, from the architectural level down to the transistor level, to reduce system power. He also shared an interesting fact about IBM’s Watson computer: It has the same computing power as the human brain, except the human brain uses 2,500 times less power.

Dr. Kim opened the final day of the conference with an insightful keynote that tied together many key SNUG themes by illustrating the challenges and solutions in designing state-of-the-art ICs. He described a consumer electronics industry surpassing $186B in 2011 and the resulting design challenges in creating next-generation 'always connected' smart devices. These challenges include 5X performance and 50x network bandwidth increases with the same power budget, extreme design complexity and intense turnaround time requirements. In offering solutions, Dr. Kim highlighted the need for advanced design techniques and manufacturing technologies, as well as the importance of collaboration among EDA, IP and foundry companies.

In addition to the technical sessions and keynotes, SNUG San Jose 2011 featured two highly successful evening events. On the first day of the conference, more than 650 users took advantage of the opportunity to engage with more than 60 companies exhibiting at the Designer Community Expo. At the Expo, users met with Synopsys and its design community partners from across the electronics industry to look at the latest solutions spanning seven categories: Compute & Design Infrastructure, Custom Design & AMS Verification, IC Design, IC Verification, IP, FPGA and System-Level Design.

The second day of SNUG wrapped with more than 700 users mixing amid air hockey games and beer gardens during the German-themed "SNUGtoberfest."

SNUG was established more than 21 years ago to create strong channel of communication for users to interact with each other and with Synopsys. Today, more than a dozen SNUG events around the world combine to make SNUG the largest user conference program in EDA. Attendees represent the world's largest semiconductor design and manufacturing companies as well as many innovative start-ups.

For more information on ongoing SNUG conferences, please visit http://snug.synopsys.com.