New Silicon Test Technology in Synopsys' TetraMAX ATPG Increases Detection of Subtle Manufacturing Defects

Reducing defective parts per million (DPPM) is a key challenge facing many design teams and is especially difficult as new types of subtle defects manifest with emerging processes nodes and FinFETs. To meet quality goals, design teams use multiple types of tests that target various defects. Until now, no available test targeted transient defects within design cells that negatively impact performance by the smallest observable amount. At established process nodes, targeting these defects enables designers to achieve very low DPPM levels required by the automotive industry and applications with similar quality standards.

Unique new slack-based cell-aware technology in TetraMAX® ATPG showcased at ITC 2014 addresses such defects by leveraging behavior information of defective cells simulated with Synopsys circuit simulators along with design performance data from the Synopsys PrimeTime static timing signoff solution. As a result, TetraMAX is capable of achieving silicon defect coverage levels not previously attainable. This new technology will be discussed and analyzed by a user at the 22nd Annual Synopsys Test Special Interest Group event in Seattle, Washington on October 20, 2014. In addition, for fast turnaround time, DFTMAX™ is linked to TetraMAX and built into Design Compiler® RTL synthesis, forming part of the Synopsys Galaxy™ Design Platform suite of tools that concurrently optimizes all design goals.

Commenting on the new capability, Bijan Kiani, vice president of marketing for the Design Group at Synopsys, noted, "We continue to advance our technology to match our customers' constant need for higher silicon test quality. The new test technology addresses the challenges of testing FinFETs and enabling low DPPM levels without impacting design goals and schedules."

The Synopsys synthesis-based test solution is comprised of DFTMAX, DFTMAX Ultra and TetraMAX for power-aware logic test and physical diagnostics; DesignWare® STAR Hierarchical System for hierarchical test of IP and cores on an SoC; DesignWare STAR Memory System® for embedded test, repair and diagnostics; Yield Explorer for design-centric yield analysis; and Camelot™ for CAD navigation. Synopsys' test solution combines Design Compiler® RTL synthesis with embedded test technology to optimize timing, power, area and congestion for test as well as functional logic, leading to faster time-to-results due to zero or minimal design iterations. The solution contains value links among the test products and across the Synopsys Galaxy Design Platform to enable faster turnaround time meeting both design and test goals, higher defect coverage and faster yield ramp.