Products + All Products + Software Integrity + Semiconductor IP + Verification + Design + Silicon Engineering
By Howard Ko, Senior Vice President & General Manager, Silicon Engineering Group
The semiconductor industry is being challenged as never before when it comes to device patterning technology. While development of new patterning techniques and resists, as well as inspection and metrology capabilities, have helped advance device scaling, new issues continue to challenge the continuation of Moore’s Law, as well as ‘More than Moore’ devices.
Economics have always been the key driving force for technology evolution in the industry. The continued push for more advanced applications and lower-cost products has been behind many familiar trends – shrinking technology nodes, ever-larger design sizes, continued growth of both optical-proximity correction (OPC) flow complexity and post-OPC file sizes, and escalating mask write times.
Today, the most significant trend in this respect is the increasing number and diversity of new materials being used for imaging. As Figure 1 shows, new technologies are being added along the axis of Moore’s Law, from the 14nm node down to 7nm. Those in red will require new materials, and are growing in number and impact with each new node. Moreover, their impact is not limited to emerging nodes.
Along the More than Moore axis, in areas such as displays, CMOS image sensors (CIS) and MEMS – where advanced designs are being developed at established nodes – these new materials are making their presence felt as well. Because the geometries are not as demanding, the challenges are less complicated, but they must still be dealt with.
Figure 1. New imaging materials impact critical patterning techniques as market trends evolve.
Figure 2. Low model predictability is emerging as the most critical patterning challenge beyond 14/10nm.The solution: rigorously tuned compact models.
Previously, creating OPC models involved utilizing conventional critical-dimension (CD)-based metrology to extract metrology data from the test pattern and CD data from the optics information provided, calibrating and fitting the data to accommodate well-understood parameters, and producing a traditional compact model. Before 28nm, this approach was sufficiently fast and accurate.
Below 28nm, however, there are many more effects that can’t be captured by using this methodology. Some examples include the physical and chemical effects that impact the shape of the resist, the resulting topology of the etch step, and other physical effects, such as flares.
When using a scanning electron microscope (SEM), the resist profile is assumed to be a regular, rectangular shape. With new resists, coatings, developer solutions, etc., the shape is impacted by such phenomena as bridging to the contours, top-loss problem due to the resist, and collapsing of the contours. Without a clean, vertical profile, CD-SEM metrology cannot identify these problems.
Rigorously tuned compact models
Working closely with customers and partners, Synopsys has developed this entirely new type of compact model, designed to address the challenges associated with complex new materials. From the start of a project, we look closely at the physics so that we have a complete understanding of all the variables before mapping it into a compact model, factoring in additional metrology data as we go.
A rigorously tuned compact (RTC) model, in essence, is still fitted to the measurement data, but by looking holistically at optics, resist, etch, advanced materials and physical effects, we have a clear picture of what that physical description should be, so we know what we’re really mapping to – rather than using assumptions, as in calibration or model fitting. Knowing the physics of the rigorous model tells you exactly what you need to map into; in turn, this will enable rigorous compact models to become more general and more predictable (see Figure 3).