Designers today face increasing process challenges at sub-20nm. Triple patterning is becoming common at 10nm, and metal fill density is more of an issue than ever before. To address these challenges, Synopsys has introduced a new version of IC Validator, release 2014.06, which offers significant new capabilities to designers confronting these sub-20nm signoff verification and In-Design issues.
New features of IC Validator include:
- Triple patterning decomposition and checking for 10nm and below designs
- New programmable extended electrical rule checking (EERC) module, which makes new checks possible
- 2X speed-up and memory reduction for LVS short detection
- Enhanced In-Design capabilities for timing-aware metal fill and fill density
- Expanded set of foundry-certified runsets
Implementing triple patterning is more difficult than double patterning, and there is no equivalent to double patterning’s odd-cycle loops for identifying violations. To overcome this, Synopsys enabled Design Rule Checking (DRC) for advanced processes at 10nm and below with a triple pattern decomposition engine that is comprehensive and extremely fast. IC Validator’s new patented technology allows graphical feedback on triple pattern color conflicts with fix guidance. This technology is already tapeout-proven on a 10nm test chip.
The new programmable EERC module in IC Validator enables designers to validate an entirely new class of mixed-mode checks that combine netlist checks with geometric checks. For example, a single rule will check the well spacing on static discharge protection devices that are identified through netlist connectivity checks. All violations are displayed in the VUE graphical debugger with full schematic to layout cross-probing.
To boost productivity for designers debugging shortened nets, Synopsys has rewritten IC Validator’s layout-vs.-schematic (LVS) core command for finding shorts between text markers. Using the new LVS core command, designers can now achieve 2X faster runtime while using 2X less memory. Synopsys has also improved the quality of the extracted layout netlist by adding enhanced hierarchical assignment heuristics that allow better placement of devices.
In-Design's timing-aware metal fill strives to minimize the timing impact of adding metal fill to a design in IC Compiler. Synopsys has enhanced the algorithm with the ability to control the spacing of fill polygons on layers above and below timing-critical signal wires. This milestone allows designers to achieve better fill densities and less timing impact than is possible with only same-layer spacing control. The In-Design auto-DRC repair (ADR) function has been extended to operate selectively on clock nets as well as signal nets. Several usability enhancements make it possible to easily control the effort level for ADR repair and to display graphical fill density and fill gradient maps.
In collaboration with our major foundry partners, the IC Validator team has mounted a concerted effort during the past year to expand Synopsys runset availability for all popular processes. IC Validator now includes support for the following major foundries:
- GlobalFoundries: 14nm to 65nm
- Intel Custom Foundry: 14nm and 22nm
- Samsung: 10nm to 28nm
- SMIC: 28nm to 180nm
- TSMC: 10nm to 350nm
- UMC: 14nm to 110nm
Customers can download IC Validator version 2014.06 from the Synopsys website using their SolvNet accounts or contact their Synopsys sales or applications consultant representatives to download the new version.
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