- 25 percent faster runtime to accelerate design schedules
- 5 percent reduction in area and leakage power for all process nodes
- Seamless Design Compiler Graphical to IC Compiler II flow delivering better correlation and quality of results (QoR)
- Tighter correlation to place-and-route at emerging process nodes, including parametric on-chip variation (POCV) support
The 2015.06 release of Synopsys’ Design Compiler® family of RTL Synthesis tools, a key component of Synopsys’ Galaxy™ Design Platform, is now available. New innovations in this release provide 25 percent faster runtime, reduce both design area and leakage power by 5 percent, and deliver improved synthesis to place-and-route correlation for emerging process nodes.
Design Compiler 2015.06 includes new optimizations that reduce design area and leakage power by 5 percent while maintaining timing QoR at all process nodes. These area and power optimizations operate on new or legacy design netlists, with or without physical information. These improvements enable an up to 20 percent reduction in area and leakage over the last three releases of Design Compiler.
This release offers significant productivity and QoR improvements when using DC Graphical and IC Compiler II. It enables a single command data transfer from DC Graphical to IC Compiler II, including all designs data, constraints and physical guidance. It provides 5 percent and 7 percent timing and area correlation between synthesis and placement and improved timing QoR when passing physical guidance to IC Compiler II. In addition, a transparent link from DC Graphical to IC Compiler II floorplanning enables early floorplan exploration within the synthesis environment.
Emerging process nodes are characterized by highly resistive wires which can lead to signal distortion that impacts layout-to-silicon correlation. Also, on-chip variation (OCV) effects are more severe and cannot be adequately addressed by margining. With the 2015.06 release of Design Compiler, the Galaxy Design Platform now supports parametric on-chip variation (POCV), a lightweight statistical margining approach to generate higher performance circuits throughout the design flow to address these challenges through more accurate signal modeling to enable tighter silicon correlation.
"Achieving smaller area, lower power and faster performance continue to be key goals for our customers designing across all process nodes," stated Bijan Kiani, vice president of marketing in Synopsys’ Design Group. “Design Compiler’s latest synthesis innovations deliver improvements for all key design metrics enabling our customers to innovate with their products while achieving superior quality of results and faster time to market."
Additional new technologies delivered by Design Compiler 2015.06 include:
- 25 percent reduction in total negative slack (TNS) for faster design closure
- Tighter timing correlation for designs at 16-nanometer and 10-nanometer
- Congestion reduction targeted for networking and other designs containing large multiplexers
- Ease of use enhancements for physically-aware multibit register inferencing without the need for user guidance
- Multibit register inferencing support in DC Explorer
The Design Compiler family addresses challenging requirements, such as performance, area, power and congestion, for designs at all process nodes. It provides designers with visualization of congested circuit regions and enables them to perform automated synthesis optimizations to minimize congestion in these areas. Design Compiler shares physical technologies with Synopsys’ IC Compiler and IC Compiler II place-and-route solutions to deliver highly correlated results for timing, area, power and routability, reducing design iterations and shaving critical schedule time. Further, Design Compiler enables designers to efficiently perform what-if analyses of various design configurations early in the design cycle to speed the development of high quality RTL and constraints and drive a faster, more convergent design flow.
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