The Accellera Systems Initiative recently honored Synopsys Fellow Janick Bergeron with its second annual Accellera Technical Excellence Award. Bergeron received the prestigious award in recognition for his contributions to Accellera's Universal Verification Methodology (UVM) standardization effort and for the many technical advancements he has brought to the field of functional verification methodology. The award was presented on February 25th during DVCon, the premier conference for discussion of the functional design and verification of electronic systems. The first recipient of Accellera's Technical Excellence Award was John Aynsley, Doulos CTO, who was recognized in 2012 for his contributions to SystemC.
For the past 10 years, Bergeron has helped drive the creation and adoption of verification methodologies through his work on Reference Verification Methodology (RVM), Verification Methodology Manual (VMM), and later UVM. Most recently, he transitioned to applying UVM to verification IP (VIP), which has become increasingly important as systems on chips (SoCs) have grown in complexity with more protocols and interfaces to verify. With Synopsys' acquisition of EVE in October 2012, Bergeron added to his charter by taking on the migration of Synopsys VIP to hardware emulation platforms and working on UVM applicability to synthesizable VIP.
In the video interview below, Bergeron talked about how critical it is to continue to evolve verification standards so the industry can maintain verification productivity despite the growing size of designs. "Standardization offers the ability to create an infrastructure and grow the ecosystem so that we can focus on higher value-added activities such as verifying the functionality of design instead of repeating the verification of standard protocols and design IP," said Bergeron. "Just as design reuse has improved productivity on the design side, verification reuse, which is enabled only through a consistent, industry-wide methodology, has enabled a similar increase in verification productivity." In the video interview below, Bergeron talked about how critical it is to continue to evolve verification standards so the industry can maintain verification productivity despite the growing size of designs. "Standardization offers the ability to create an infrastructure and grow the ecosystem so that we can focus on higher value-added activities such as verifying the functionality of design instead of repeating the verification of standard protocols and design IP," said Bergeron. "Just as design reuse has improved productivity on the design side, verification reuse, which is enabled only through a consistent, industry-wide methodology, has enabled a similar increase in verification productivity."
