The Accellera Systems Initiative recently honored Synopsys Fellow Janick Bergeron with its second annual Accellera Technical Excellence Award. Bergeron received the prestigious award in recognition for his contributions to Accellera's Universal Verification Methodology (UVM) standardization effort and for the many technical advancements he has brought to the field of functional verification methodology. The award was presented on February 25th during DVCon, the premier conference for discussion of the functional design and verification of electronic systems. The first recipient of Accellera's Technical Excellence Award was John Aynsley, Doulos CTO, who was recognized in 2012 for his contributions to SystemC.
For the past 10 years, Bergeron has helped drive the creation and adoption of verification methodologies through his work on Reference Verification Methodology (RVM), Verification Methodology Manual (VMM), and later UVM. Most recently, he transitioned to applying UVM to verification IP (VIP), which has become increasingly important as systems on chips (SoCs) have grown in complexity with more protocols and interfaces to verify. With Synopsys' acquisition of EVE in October 2012, Bergeron added to his charter by taking on the migration of Synopsys VIP to hardware emulation platforms and working on UVM applicability to synthesizable VIP.
In the video interview below, Bergeron talked about how critical it is to continue to evolve verification standards so the industry can maintain verification productivity despite the growing size of designs. "Standardization offers the ability to create an infrastructure and grow the ecosystem so that we can focus on higher value-added activities such as verifying the functionality of design instead of repeating the verification of standard protocols and design IP," said Bergeron. "Just as design reuse has improved productivity on the design side, verification reuse, which is enabled only through a consistent, industry-wide methodology, has enabled a similar increase in verification productivity." In the video interview below, Bergeron talked about how critical it is to continue to evolve verification standards so the industry can maintain verification productivity despite the growing size of designs. "Standardization offers the ability to create an infrastructure and grow the ecosystem so that we can focus on higher value-added activities such as verifying the functionality of design instead of repeating the verification of standard protocols and design IP," said Bergeron. "Just as design reuse has improved productivity on the design side, verification reuse, which is enabled only through a consistent, industry-wide methodology, has enabled a similar increase in verification productivity."
Janick Bergeron, Synopsys Fellow
UVM is an example of how a standard can evolve by unifying what used to be disparate methodologies into a single verification language and method for putting things together. According to Bergeron, "UVM enables an ecosystem of VIP, tools, training and consulting services using a common methodology that is scalable and can be plug-and-play." Synopsys is an active participant in this ecosystem, offering all of the above to help SoC providers verify and debug their increasingly complex SoCs while meeting their aggressive time- to-market windows.
Bergeron said receiving the Accellera award has been a flattering and humbling experience. "I've been writing, codifying and training on verification methodology for almost 20 years now. I see it as a culmination of an effort that initially was not seen as being that big of a problem, but has now emerged as the biggest problem. It makes it all worthwhile."
Bergeron's vision for future standards includes continuing to secure increased input from users during the standardization process, much like the way UVM was created for the industry. "With the ever-increasing pace at which a design must be verified and created, the long, slow-moving process of creating standards is difficult to maintain. Having standards that can adapt quickly to problems that emerge will become necessary," said Bergeron.
Bergeron is the author of the best-selling Verification Methodology Manual for SystemVerilog and Writing Testbenches: Functional Verification of HDL Models. He is also the founder and moderator of the Verification Guild forum and writes the verification methodology blog Verification Martial Arts. Prior to joining Synopsys, Bergeron worked on verification methodology at Qualis Design Corporation and Nortel. He holds a Masters degree in Electrical Engineering from the University of Waterloo, a Bachelor of Science degree in Engineering from the Université du Québec, and an MBA degree granted through the University of Oregon.
Synopsys congratulates Bergeron on this prestigious award and eagerly anticipates his next achievements in the evolving field of verification methodology!
For more information, please visit the following link: Janick Bergeron Receives Accellera Systems Initiative Technical Excellence Award