2014.12 Release of IC Validator Delivers In-Design with IC Compiler II and Features Programmable EERC Expansion

Designers are continually seeking differentiation so that their product will win the design socket, the major infrastructure contract, or be the next portable design that consumers put in their pocket. At the same time, system-on-chip (SoC) designs not only must conform to extensive foundry fabrication rules but also need to achieve high die yield from every wafer. Synopsys' physical verification plays an important role in the story of product concept to product delivery and success. IC Validator DRC/LVS and In-Design physical verification provide ever faster and more efficient ways to validate design implementation and help ensure physical signoff at established and advanced process nodes.

Faced with these tremendous pressures, SoC designers should appreciate the new 2014.12 release of the Synopsys IC Validator physical verification tool and its companion technology, In-Design [see Figure 1]. Whether the challenge is to derive additional differentiation at existing nodes or begin designing at the most recent emerging node, IC Validator DRC/LVS and In-Design offer new features to meet those challenges head on. The 2014.12 IC Validator release also marks the first release that enables In-Design in the IC Compiler™ II place and route solution, which delivers 10X faster design productivity.

Figure 1: In-Design physical verification with Synopsys' IC Compiler and IC Compiler II place and route solutions enables users to eliminate late-stage surprises and manual repairs, accelerating turnaround time and resulting in faster design closure.

Figure 1: In-Design physical verification with Synopsys' IC Compiler and IC Compiler II place and route solutions enables users to eliminate late-stage surprises and manual repairs, accelerating turnaround time and resulting in faster design closure.

Figure 2: In-Design metal fill insertion minimizes the growing impact of fill on timing, particularly at emerging nodes.

Figure 2: In-Design metal fill insertion minimizes the growing impact of fill on timing, particularly at emerging nodes.

The ability of a chip to stand up to expected and unexpected electrical events is an important differentiation that is enabled by electrical rule checking (ERC). In the past, these checks were performed manually and were not comprehensive as a result. Programmable extended electrical rule checking (EERC) in IC Validator 2014.12 enables fast and easy compliance with electrical checks and guidelines. The Programmable EERC module enables electrical rule checks to perform topology-based schematic or layout netlist analysis as well as the ability to then move into the geometric domain to perform checks on the associated shapes. This capability is essential for electrostatic discharge (ESD) checking, netlist domain checking, mixed-mode checking, cross domain checking, latch-up analysis, voltage-dependent spacing rules, the analysis of geometric symmetry in analog circuits and other previously uncheckable rules. In addition to the ability of the PXL runset language to facilitate succinct capture of complex electrical rules, Synopsys Programmable EERC users benefit from a new tagging, propagation and caching infrastructure to efficiently deal with hierarchy in large designs while minimizing the memory footprint.

Through its programmable EERC capabilities, the 2014.12 release of IC Validator with In-Design technology enables higher design cycle productivity, better profitability through fabrication yield and better long-term product robustness. In addition to the major components of this new release already noted, there are many other important features:

  • IC Validator adds 10-nm support to meet 10-nm foundry requirements. One such enabling technology is the robust N-layer infrastructure in place to smoothly transition decomposition checking for double, triple, quadruple and future mask layer support. With N-layer support, IC Validator is already preparing the path to 7-nm readiness and beyond.
  •  Other innovations for all users include enhanced LVS debugging ease with the addition of a full CDL / SPICE-based LVS flow, allowing the user to stay in that domain for all their LVS debug work.
  • In-Design non-track-based as well as track-based metal fill both add density-aware fill to meet both per layer and combined layer density requirements. New density visualization includes both density heat and density gradient maps to view density variations in adjacent regions.
  • IC Validator enjoys comprehensive and ever-growing foundry runset support at GLOBALFOUNDRIES, Intel Custom Foundry, Samsung, SMIC, TSMC and UMC.

Availability

Customers can download IC Validator version 2014.12 from the Synopsys website using their SolvNet accounts or contact their Synopsys sales or applications consultant representatives to download the new version.

Learn more about IC Validator