SNUG Silicon Valley 2022 Announcement

Driven by COVID-19 concerns, the SNUG Silicon Valley 2022 conference scheduled for March 30-31 in Santa Clara will now be conducted virtually in its entirety. Original plans were to conduct SNUG as a hybrid conference with both in-person and online participation. But with recent developments, and because the safety and well-being of conference participants is our priority, this change is appropriate.

This is of course disappointing as we were all looking forward to once again convening in person, but we believe moving to a fully virtual format is the right decision. And in some ways, little will change. SNUG will still take place on March 30-31, 2022 and will offer user presentations, keynote addresses, panels and tutorials. 

The SNUG team remains committed to delivering an exciting conference, driven by the always innovative Synopsys community. Thank you and stay healthy. 

Call for Content Info

The Call for Content is now closed. Synopsys users will soon be able to register to virtually attend SNUG Silicon Valley, to be held on March 30-31, 2022.

For more than three decades, SNUG has connected users and technical experts to network and share best practices for tackling design and verification challenges. As a SNUG presenter, you will increase your visibility in the Synopsys user community. In addition to the professional recognition, you will be eligible for awards (please check your company’s gift acceptance policy).


We have a preliminary list of topics to get you started, but don't let that limit your ideas or innovation:


  • Improving productivity and achieving faster quality-of-results with AI and machine learning in Synopsys design flows
  • From the data center to the edge – enabling highest performance AI designs with Synopsys implementation solutions
  • Architectural exploration and early software development with virtual/physical prototyping
  • Formal verification of data path designs
  • Using emulation for AI software stack validation
  • AI-enabled productivity and performance innovation
  • Using virtual test environments for network system validation
  • Using AI-ready IP to meet processing, memory, and connectivity requirements for deep learning applications
  • The challenges of designing and integrating AI accelerators
Show topics 


  • Accelerating automotive software development and validation with virtual prototyping
  • Complete functional safety verification with fault simulation, formal and static verification
  • High reliability design techniques for automotive designs
  • Hardware security verification
  • Implementing safety critical designs for automotive applications
  • Designing ISO 26262 required in-system test using Synopsys tools
  • Accelerating ISO 26262 certification with ASIL-ready certified IP
Show topics 


  • Addressing analog, custom digital or memory design verification turn-around time bottlenecks with heterogenous compute acceleration
  • RF analysis of RFIC or analog periodic circuits using FineSim
  • Ensuring AMS design robustness with advanced variability analysis
  • Minimizing design margins with integrated power/signal net electromigration/IR drop analysis
  • Improving AMS design robustness with analog circuit ERC
  • Best practices in mixed-signal verification with a digital verification methodology using CustomSim and VCS
  • Verifying power and signal integrity for multi-gigabit circuits with HSPICE
  • Accelerating pre-layout design centering & optimization
  • Custom layout productivity gains from using Custom Compiler’s visually assisted automation (symbolic editor, interactive routing, template-based design)
  • Mixed custom/digital implementation productivity gains from using Custom Compiler co-design with IC Compiler II or Fusion Compiler
  • Faster analog design closure using Custom Compiler early-electrical analysis with StarRC (in-design RC and EM, partial-layout simulation flow)
Show topics 


  • Trading off performance vs. cost for design or verification in a cloud environment
  • Security concerns and best practices in migrating from on-premises to cloud for design and verification
  • Allocation and usage of cloud resources for library characterization, simulation, timing analysis and parasitic extraction
  • Maximizing available resources with ICV elastic CPU usage
  • Impacts on design size partition for physical implementation in a cloud environment
  • Leveraging tool runtime scalability in the cloud; what worked best
Show topics 


  • Raising the bar on achieved PPA with a Fusion Compiler convergent flow
  • Optimal design flow for digital implementation of advanced node designs
  • Accelerating time-to-results for large designs with Design Compiler Graphical and IC Compiler II
  • Shift-left convergence with RTL Architect by improving constraints and RTL restructuring
  • How to achieve optimized performance, power and area for Arm CPUs
  • Using parallel processing to accelerate physical and full chip timing signoff
  • Accelerating full chip turn-around time for large designs using IC Validator physical signoff
  • Optimization techniques for low-power IoT designs
  • Early time-based peak power analysis with PrimePower using RTL-based vectors
  • Using physically aware ECO capabilities to improve PPA and accelerate timing closure
  • Design implementation on the cloud
  • Extending the envelope of Moore’s law with 3D / 2.5D IC design; lessons learned
Show topics 


  • Low-power design for smart edge devices
  • AI-driven power considerations
  • The quest for energy efficiency: evaluating hardware and software approaches
  • Transistor-level vs. system-level energy optimization
  • Is Low Low Enough? The Special Power Demands of Crypto Chips
Show topics 


  • Getting to fast physical verification at 7nm and below
  • Leveraging ICV multi-CPU scalability for fast time-to-results
  • Maximizing available resources with ICV elastic CPU usage
  • Dirty design handling during SoC integration to minimize runtime and maximize productivity
  • Shift-left physical verification analysis and repair utilizing fusion technology in IC Compiler II and Fusion Compiler
Show topics 


  • Strategies to Reduce Chip Vulnerabilities Through Hardware, IP or Software Approaches
  • The Role of an SoC-based Root of Trust for Security
  • How to Leverage Standards to Enhance Safety and Security
  • Hardware and Software Approaches to Implementing Functional Safety
Show topics 


  • How 3DIC design changes signoff
  • AI algorithms and their impact on signoff
  • Balancing timing, power, power/signal integrity closure
Show topics 


  • Success with early RTL analysis, physically aware and area saving DFT, higher defect detection, lower pattern count/test time, faster and volume diagnostics
  • Use of software analytics for accelerating product introduction as well improving yield, test times and quality during high volume production
  • Highlighted SoC application areas include AI, automotive, mobile and processors
Show topics 


  • Interface IP such as 112G Ethernet, Die-to-Die, PCIe 5.0, DDR5/LPDDR5, etc.
  • Embedded ARC processors & embedded vision processors
  • OTP NVM, embedded memories & logic libraries in advanced FinFET processes
  • Integration of IP into high-performance computing, automotive, AI/ML or IoT designs
  • Integration of PVT sensor IP monitors and subsystems for enhanced device screening, power and performance optimization, and enhanced field performance/security
Show topics 


  • Accelerating software bring-up with emulation and prototyping
  • Software-driven power analysis for GPUs and AI
  • Prototyping with real-world interfaces
  • Large complexity prototyping
  • Pre-silicon networking system validation
  • SoC performance validation using emulation
  • Trust and hardware security verificationDFT-driven emulation
  • The value of emulation for mission-critical designs
  • Insights from power emulation
  • Prototyping approaches for 2.5/3D heterogeneous integration
  • The insights available from prototyping
Show topics 


  • Faster and better convergence using formal methods
  • Verification coverage planning and closure
  • Best practices for static verification (Lint/CDC/RDC/SDC/LP) signoff
  • Accelerating verification and debug for advanced protocols
  • Innovations in verification methodology for optimized performance
Show topics 

Important Dates

All Content Submissions to SNUG Silicon Valley are Presentation-Only Format

Call for Content Opens  | October 12, 2021

Call for Content Closes  | Extended to December 8, 2021

Preliminary Acceptance Notification  | December 17, 2021

Draft Presentation Due  | January 14, 2022

Final Acceptance & Presentation Spots Awarded  | January 31, 2022

Final Presentation Due | February 28, 2022

SNUG Silicon Valley 2022  |  March 30-31, 2022

Copyright Statement

Please carefully read the following notice before submitting your written materials to the SNUG program.

By submitting materials to the SNUG program, you and your employer authorize Synopsys  to reproduce, publish and distribute the submitted materials, including the right to take or records notes, quotes and other text, company and/or product logos, graphics, images, audio and/or video and other materials, as applicable(including any names, voices, likenesses or biographical information therein, (the “Materials”) and post them on the SNUG website and Virtual platform for access by Synopsys employees, contractors, and licensees. This applies to SNUG Silicon Valley and all other SNUG events worldwide that are taking place in 2022. ​

This agreement is not intended to transfer the ownership of any intellectual property rights contained in the Materials. Any personally identifiable information of any individuals contained in the Materials will be handled in accordance with Synopsys’ Privacy Policy, available for review at and ​

Synopsys shall reproduce any copyright or other legal notices you include in your submitted materials. Other than described herein, Synopsys will not otherwise use your submitted materials for product marketing purposes without first obtaining your separate written consent. ​

By agreeing to the above, you provide your approval of the terms of this letter and confirm you are authorized to sing on behalf of your company. ​ In addition to the copyright statement above all presenters will be required to submit a signed video release to Synopsys along with their final presentation slides to verify approval to utilize session recording.  

If you have any questions, please contact the SNUG team before submitting your proposal. 

Show copyright statement 

Contact Information

If you have any questions, please contact the SNUG team