SNUG UK 2014 Proceedings

A3 - High-Performance Implementation I

Use of Concurrent Clock and Data Optimization in Hardening Processor Cores to 1GHz
Author(s): Richard White, Andrew Miles - Sondrel Ltd.

A4 - Verification I

Certitude Advanced Tips
Author(s): Jean-Francois Vizier - Dialog Semiconductor

Using Certitude for Relative Functional Qualification of a Re-usable Testbench
Author(s): Satwinder Singh - Infineon Technologies

A5 - Analog Mixed-Signal Verification I

How to Write an Optimum Verilog-A Model (Best Paper Award, Technical Committee Award)

Author(s): Peter Grove - Dialog Semiconductor

A6 - Signoff-Driven Optimisation I

PrimeTime Signoff and ECO on a SOC with 70+Million Placeable Cells in 28nm
Author(s): Gianvito Lorusso, Stephane Cauneau, Iain Stickland, Shuhua Li, Min Ren, Qing Yuan - Sondrel

B2 - Low Power Implementation II

Low-Power Implementation of Complex MIPS Cores
Author(s): Maya Mohan, Nagesh Sakhamuru - Imagination Technologies

B3 - High-Performance Implementation II

IC Compiler II and the Power of 10x: A Product Walk-through
Author(s): Saleem Haider, Henry Sheng - Synopsys Inc.

B4 - Verification II

A Simplified Approach to Generating Functional Coverage
Author(s): Neil Bulman, Aditya Pagonda - Broadcom

B6 - Signoff Driven Optimisation II

Reducing Timing ECO Loops using Physically Aware ECO (3rd Place - Best Paper)

Author(s):

Static Timing Analysis - Sign-off Timing Margins for Leading-Edge Processes
Author(s): Andy Hulbert - Broadcom Corporation

C1 - FPGA Implementation and FPGA-based Prototyping III

Safety 1st, Infineon implements ProtoLink's FPGA Fault Injection to Provide Safer Roads (Technical Committee Award Honorable Mention)

Author(s): Martin Terry, Mike Dunk - Infineon Technologies

C2 - Low Power Verification I

The Challenges of Low Power Design: A System-on-Chip with 152 Power Domains
Author(s): David Bean - Ericsson

C3 - High-Performance Implementation III

Adding Interface Transparency to Chip-level Optimisation
Author(s):

C4 - Verification III

Easier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption
Author(s): John Aynsley, David Long, Christoph Sühnel - Doulos

Improving Data Monitoring in UVM - Tips and Recommendations
Author(s): Yogish Sekhar - Dialog Semiconductor

Reverse Gear: Re-imagining Randomization using the VCS Constraint Solver
Author(s): Jonathan Bromley, Paul Marriott - Verilab

C6 - Design for Test I

Scan Insertion and ATPG for C-gate Based Asynchronous Designs (1st Place - Best Paper)

Author(s): David Lloyd, Richard Illman - Dialog Semiconductor

Transitioning from DFTMAX to DFTMAX Ultra (2nd Place - Best Paper)

Author(s): Richard Illman - Dialog Semiconductor

Tutorials

A1 - FPGA Implementation and FPGA-based Prototyping I

Automating SoC RTL to Operational Prototype
Author(s): Andy Jolley - Synopsys Ltd.

A2 - Low Power Implementation I

Verdi Signoff-LP: Next-Generation Low-Power Static Verification
Author(s): Tom Ryan - Synopsys Ltd.

A3 - High-Performance Implementation I

Emerging Node Design with IC Compiler
Author(s): Alec Cobb - Synopsys Ltd.

A5 - Analog Mixed-Signal Verification I

Low-Power and Simulation Performance in Mixed-Signal
Author(s): Peter Thompson - Synopsys Inc.

A6 - Signoff-Driven Optimisation I

Pimp My Run - Maximising Performance in Signoff STA
Author(s): Simon Bloyce - Synopsys Ltd.

B1 - FPGA Implementation and FPGA-based Prototyping II

Emulation and Prototyping of Imagination GPUs using ZeBu and HAPS
Author(s): Colin McKellar - Imagination Technologies, Andy Jolley - Synopsys Ltd.

Putting IP Prototyping on the Fast Track with HAPS Developer eXpress
Author(s): Michael Posner - Synopsys Inc.

B5 - Analog Mixed-Signal Verification II

Transistor-Level Static Circuit Analysis, an ERC Solution for Low-Power Custom Digital, Memory, and Analog IP Designs
Author(s): Luong Nguyen - Synopsys France

When Bandgaps Regress: Solving the Challenges of AMS Verification
Author(s): Paul Chapman - Synopsys Ltd.

C1 - FPGA Implementation and FPGA-based Prototyping III

Efficient Debug and Deployment of FPGA Prototyping Systems
Author(s): Frank McMillan - Synopsys Ltd.

C2 - Low Power Verification I

Low-Power Enhancements in the Mixed-Signal Area
Author(s): Peter Thompson - Synopsys Inc.

C5 - Mixed-Signal & Digital Implementation I

Hands-on Galaxy Custom Router Workshop with Competition and Prize Draw
Author(s): Chris Shaw - Synopsys Inc., Damian Roberts - Synopsys Ltd.

Combo

C3 - High-Performance Implementation III

Use of Routing Guides in a Highly Congested Design
Author(s): Andrew Miles - Sondrel, Martyn Brown - Synopsys Ltd.

User Presentation

B2 - Low Power Implementation II

Addressing Challenges Created by the Internet-of-things
Author(s): Andrew Crowe - Ensilica

B3 - High-Performance Implementation II

Using IC Compiler II for Design Planning Next Generation Large & Complex Graphics Cores
Author(s): Nigel Winterbottom - Imagination Technologies

B4 - Verification II

Vertical Reuse of Block-Level Testbenches – Make it Happen!
Author(s): Aditya Pagonda - Broadcom