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SNUG UK 2014 Proceedings

2016  |  2015  |  2014  |  2013  

Complete Proceedings

User Papers and Presentations
A2 - Low Power Implementation I
Power Intent Constraints, how Adoption of IEEE Standards Improves our IP and Design Methodology
Author(s): Stuart Riches - ARM Ltd.
PaperPresentation
A3 - High-Performance Implementation I
Use of Concurrent Clock and Data Optimization in Hardening Processor Cores to 1GHz
Author(s): Richard White, Andrew Miles - Sondrel Ltd.
PaperPresentation
A4 - Verification I
Certitude Advanced Tips
Author(s): Jean-Francois Vizier - Dialog Semiconductor
PaperPresentation

Using Certitude for Relative Functional Qualification of a Re-usable Testbench
Author(s): Satwinder Singh - Infineon Technologies
PaperPresentation
A5 - Analog Mixed-Signal Verification I
How to Write an Optimum Verilog-A Model (Best Paper Award, Technical Committee Award)
Author(s): Peter Grove - Dialog Semiconductor
PaperPresentation
A6 - Signoff-Driven Optimisation I
PrimeTime Signoff and ECO on a SOC with 70+Million Placeable Cells in 28nm
Author(s): Gianvito Lorusso, Stephane Cauneau, Iain Stickland, Shuhua Li, Min Ren, Qing Yuan - Sondrel
PaperPresentation
B2 - Low Power Implementation II
Low-Power Implementation of Complex MIPS Cores
Author(s): Maya Mohan, Nagesh Sakhamuru - Imagination Technologies
Presentation
B3 - High-Performance Implementation II
IC Compiler II and the Power of 10x: A Product Walk-through
Author(s): Saleem Haider, Henry Sheng - Synopsys Inc.
B4 - Verification II
A Simplified Approach to Generating Functional Coverage
Author(s): Neil Bulman, Aditya Pagonda - Broadcom
PaperPresentation
B6 - Signoff Driven Optimisation II
Reducing Timing ECO Loops using Physically Aware ECO (3rd Place - Best Paper)
Author(s):
PaperPresentation

Static Timing Analysis - Sign-off Timing Margins for Leading-Edge Processes
Author(s): Andy Hulbert - Broadcom Corporation
PaperPresentation
C1 - FPGA Implementation and FPGA-based Prototyping III
Safety 1st, Infineon implements ProtoLink's FPGA Fault Injection to Provide Safer Roads (Technical Committee Award Honorable Mention)
Author(s): Martin Terry, Mike Dunk - Infineon Technologies
PaperPresentation
C2 - Low Power Verification I
The Challenges of Low Power Design: A System-on-Chip with 152 Power Domains
Author(s): David Bean - Ericsson
PaperPresentation
C3 - High-Performance Implementation III
Adding Interface Transparency to Chip-level Optimisation
Author(s):
PaperPresentation
C4 - Verification III
Easier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption
Author(s): John Aynsley, David Long, Christoph Sühnel - Doulos
PaperPresentation

Improving Data Monitoring in UVM - Tips and Recommendations
Author(s): Yogish Sekhar - Dialog Semiconductor
PaperPresentation

Reverse Gear: Re-imagining Randomization using the VCS Constraint Solver
Author(s): Jonathan Bromley, Paul Marriott - Verilab
PaperPresentation
C6 - Design for Test I
Scan Insertion and ATPG for C-gate Based Asynchronous Designs (1st Place - Best Paper)
Author(s): David Lloyd, Richard Illman - Dialog Semiconductor
PaperPresentation

Transitioning from DFTMAX to DFTMAX Ultra (2nd Place - Best Paper)
Author(s): Richard Illman - Dialog Semiconductor
PaperPresentation
Tutorials
A1 - FPGA Implementation and FPGA-based Prototyping I
Automating SoC RTL to Operational Prototype
Author(s): Andy Jolley - Synopsys Ltd.
Tutorial
A2 - Low Power Implementation I
Verdi Signoff-LP: Next-Generation Low-Power Static Verification
Author(s): Tom Ryan - Synopsys Ltd.
Tutorial
A3 - High-Performance Implementation I
Emerging Node Design with IC Compiler
Author(s): Alec Cobb - Synopsys Ltd.
Tutorial
A5 - Analog Mixed-Signal Verification I
Low-Power and Simulation Performance in Mixed-Signal
Author(s): Peter Thompson - Synopsys Inc.
Tutorial
A6 - Signoff-Driven Optimisation I
Pimp My Run - Maximising Performance in Signoff STA
Author(s): Simon Bloyce - Synopsys Ltd.
Tutorial
B1 - FPGA Implementation and FPGA-based Prototyping II
Emulation and Prototyping of Imagination GPUs using ZeBu and HAPS
Author(s): Colin McKellar - Imagination Technologies, Andy Jolley - Synopsys Ltd.
Tutorial

Putting IP Prototyping on the Fast Track with HAPS Developer eXpress
Author(s): Michael Posner - Synopsys Inc.
Tutorial
B5 - Analog Mixed-Signal Verification II
Transistor-Level Static Circuit Analysis, an ERC Solution for Low-Power Custom Digital, Memory, and Analog IP Designs
Author(s): Luong Nguyen - Synopsys France
Tutorial

When Bandgaps Regress: Solving the Challenges of AMS Verification
Author(s): Paul Chapman - Synopsys Ltd.
Tutorial
C1 - FPGA Implementation and FPGA-based Prototyping III
Efficient Debug and Deployment of FPGA Prototyping Systems
Author(s): Frank McMillan - Synopsys Ltd.
Tutorial
C2 - Low Power Verification I
Low-Power Enhancements in the Mixed-Signal Area
Author(s): Peter Thompson - Synopsys Inc.
Tutorial
C5 - Mixed-Signal & Digital Implementation I
Hands-on Galaxy Custom Router Workshop with Competition and Prize Draw
Author(s): Chris Shaw - Synopsys Inc., Damian Roberts - Synopsys Ltd.
Tutorial
Combo
C3 - High-Performance Implementation III
Use of Routing Guides in a Highly Congested Design
Author(s): Andrew Miles - Sondrel, Martyn Brown - Synopsys Ltd.
Tutorial
User Presentation
B2 - Low Power Implementation II
Addressing Challenges Created by the Internet-of-things
Author(s): Andrew Crowe - Ensilica
Presentation
B3 - High-Performance Implementation II
Using IC Compiler II for Design Planning Next Generation Large & Complex Graphics Cores
Author(s): Nigel Winterbottom - Imagination Technologies
B4 - Verification II
Vertical Reuse of Block-Level Testbenches – Make it Happen!
Author(s): Aditya Pagonda - Broadcom
Presentation
Silicon Valley 2017 Keynote

Dr. Peter Stone on “Learning and Multiagent Reasoning for Autonomous Robots”

Contact the SNUG Operations team for proceedings prior to 2013

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