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Tutorials |
TA2 - Physical Implementation |
Emerging Node Design with IC Compiler II / IC Validator, Accelerating Time-to-Market with Class Leading QoR Author(s): Jocelyn Lee - Synopsys |
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Managing Metal Fill and Its Impact on Your Design - Track Based Metal Fill with IC Compiler II and IC Validator In-Design Author(s): Roy Huang - Synopsys |
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TB1 - STA/ECO |
Quick Timing Closure and Power Improvement with PrimeTime ECO Author(s): Robert Lin - Synopsys |
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TB2 - Software Quality and Security |
Synopsys SIG Solutions for Software Quality and Security Author(s): Eric Lei - Synopsys |
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TC1 - Automotive |
Synopsys Automotive Solutions ISO26262 Safety and Security Author(s): Jeff Hutton - Synopsys |
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TC2 - Verification |
Key Techniques to Speed-up Debug and Verification Closure – Recent Innovations in Verdi Author(s): Rich Chang - Synopsys |
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TD1 - AMS Simulation |
AMS Verification Solution From CustomSim, VCS-AMS Simulation to Verdi-AMS Debugging Author(s): Eric Tsai - Synopsys |
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TD2 - AMS Simulation |
Achieve High Quality Design with HSPICE, FineSim SPICE, and Custom WaveView ADV for Signal Integrity and Waveform Post-Processing Author(s): Neil Chang - Synopsys |
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Automatic Eye-Diagram Analysis and Jitter Measurement Using Custom WaveView ADV Author(s): Eugene Lee - Synopsys |
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Simulation and Analysis Environment (SAE) Author(s): Jason Chang - Synopsys |
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TE1 - Prototyping |
Multi-FPGA Debug Strategy with Synopsys Physical Prototyping Platform -- ProtoCompiler and HAPS-80 Systems Author(s): Peter Zhang - Synopsys |
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TE2 - Prototyping/System |
Adapt, Port, and Integrate Quickly – Prototyping the Right Way Author(s): Ralph Grundler - Synopsys |
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UPF 3.0 for Early, System-Level Power Analysis of SoCs with Micron DDR Memories Author(s): Sylvain Bayon de Noyer - Synopsys |
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WA1 - Implementation |
High-Performance, Energy Efficient ARM® Cortex®-A73 Implementation in TSMC 16FF+ Process Technology Using Synopsys Galaxy™ Design Platform Author(s): Mike Montana - Synopsys; John Ronco - ARM |
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WA2 - Implementation |
Best Practices for a Performance and Area Focused Implementation of High-Performance GPUs Using Galaxy Design Platform Author(s): Daniel Biset - Synopsys |
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WA3 - Physical Implementation |
Floorplanning Large Blocks Using IC Compiler II Author(s): Daniel Biset - Synopsys |
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IC Compiler II Technologies to Meet Aggressive Performance Power and Area (PPA) Goals on Advanced Designs Author(s): Daniel Biset - Synopsys |
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WB3 - Test |
Address Testability Issues Early with SpyGlass® DFT ADV RTL Testability Analysis Author(s): Anthony Joseph - Synopsys |
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WC2 - Verification |
Essential Ingredients of Formal Based Verification Signoff Author(s): Feng Huang - Synopsys |
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WC3 - Verification |
Advanced Simulation Author(s): Rich Chang - Synopsys |
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SpyGlass® RTL Signoff - Static Verification Solution Author(s): Shailandar Sachdeva - Synopsys |
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WD3 - Custom Design |
Top Down Schematic Driven Layout Flow Author(s): Ken Chuang - Synopsys |