• Silicon Design & Verification Products
  • Solutions
  • Resources
  • Services
  • Community
  • Training
  • Silicon IP Products
  • Solutions
  • Resources
  • Services
  • Community
Contact Us
Contact Us
Contact Us
  • Software Integrity
  • Tools & Services
  • Training & Education
  • Solutions
  • Resources
  • Support
  • Partners
Contact Sales
Contact Sales
Contact Sales
Contact Sales
Contact Sales
  • About Us
Discover
+ Silicon Design & Verification + Silicon IP + Software Integrity + About Us
Support
SolvNet Software Integrity
Global SItes
日本サイ ト 中文网站 中文網站 Сайт Россия

SNUG Taiwan 2016 Proceedings

2018 | 2017 | 2016 | 2015 | 2014 | 2013  

Complete Proceedings

User Papers and Presentations
TB1 - STA/ECO
How To Do Easy ECO for DFFs' Default Values Change Without Dummy Cells?
Author(s): Hung-Ta Sung - Powerchip
PaperPresentation

Incremental Signoff Features in Physical-Aware Timing ECO Flow Assessment (Honorable Mention)
Author(s): Tsung-Han Wu, Robert Lee - MediaTek
PaperPresentation

POCV: The Total OCV Solution from Synthesis, Implementation to Sign-off
Author(s): Yi-Wei Chen - MediaTek
PaperPresentation
TC2 - Verification
An Efficient Methodology to Achieve Accurate IR Analysis in Early Stage (Best Paper Award)
Author(s): Yung-Jen Chen - Realtek
PaperPresentation
WC2 - Verification
Equivalence Checking for SPICE Netlist and IO Macro Model (Best Paper Award)
Author(s): Shang-Wei Tu - MediaTek
PaperPresentation

Low Power Verification for Complex IO Macro Power Relation
Author(s): Tsu-Ting Shen, Yu-Juei Chen, Shang-Wei Tu - MediaTek; Himanshu Bhatt - Synopsys
PaperPresentation
Tutorials
TA2 - Physical Implementation
Emerging Node Design with IC Compiler II / IC Validator, Accelerating Time-to-Market with Class Leading QoR
Author(s): Jocelyn Lee - Synopsys
Tutorial

Managing Metal Fill and Its Impact on Your Design - Track Based Metal Fill with IC Compiler II and IC Validator In-Design
Author(s): Roy Huang - Synopsys
Tutorial
TB1 - STA/ECO
Quick Timing Closure and Power Improvement with PrimeTime ECO
Author(s): Robert Lin - Synopsys
Tutorial
TB2 - Software Quality and Security
Synopsys SIG Solutions for Software Quality and Security
Author(s): Eric Lei - Synopsys
Tutorial
TC1 - Automotive
Synopsys Automotive Solutions ISO26262 Safety and Security
Author(s): Jeff Hutton - Synopsys
Tutorial
TC2 - Verification
Key Techniques to Speed-up Debug and Verification Closure – Recent Innovations in Verdi
Author(s): Rich Chang - Synopsys
Tutorial
TD1 - AMS Simulation
AMS Verification Solution From CustomSim, VCS-AMS Simulation to Verdi-AMS Debugging
Author(s): Eric Tsai - Synopsys
Tutorial
TD2 - AMS Simulation
Achieve High Quality Design with HSPICE, FineSim SPICE, and Custom WaveView ADV for Signal Integrity and Waveform Post-Processing
Author(s): Neil Chang - Synopsys
Tutorial

Automatic Eye-Diagram Analysis and Jitter Measurement Using Custom WaveView ADV
Author(s): Eugene Lee - Synopsys
Tutorial

Simulation and Analysis Environment (SAE)
Author(s): Jason Chang - Synopsys
Tutorial
TE1 - Prototyping
Multi-FPGA Debug Strategy with Synopsys Physical Prototyping Platform -- ProtoCompiler and HAPS-80 Systems
Author(s): Peter Zhang - Synopsys
Tutorial
TE2 - Prototyping/System
Adapt, Port, and Integrate Quickly – Prototyping the Right Way
Author(s): Ralph Grundler - Synopsys
Tutorial

UPF 3.0 for Early, System-Level Power Analysis of SoCs with Micron DDR Memories
Author(s): Sylvain Bayon de Noyer - Synopsys
Tutorial
WA1 - Implementation
High-Performance, Energy Efficient ARM® Cortex®-A73 Implementation in TSMC 16FF+ Process Technology Using Synopsys Galaxy™ Design Platform
Author(s): Mike Montana - Synopsys; John Ronco - ARM
Tutorial
WA2 - Implementation
Best Practices for a Performance and Area Focused Implementation of High-Performance GPUs Using Galaxy Design Platform
Author(s): Daniel Biset - Synopsys
Tutorial
WA3 - Physical Implementation
Floorplanning Large Blocks Using IC Compiler II
Author(s): Daniel Biset - Synopsys
Tutorial

IC Compiler II Technologies to Meet Aggressive Performance Power and Area (PPA) Goals on Advanced Designs
Author(s): Daniel Biset - Synopsys
Tutorial
WB3 - Test
Address Testability Issues Early with SpyGlass® DFT ADV RTL Testability Analysis
Author(s): Anthony Joseph - Synopsys
Tutorial
WC2 - Verification
Essential Ingredients of Formal Based Verification Signoff
Author(s): Feng Huang - Synopsys
Tutorial
WC3 - Verification
Advanced Simulation
Author(s): Rich Chang - Synopsys
Tutorial

SpyGlass® RTL Signoff - Static Verification Solution
Author(s): Shailandar Sachdeva - Synopsys
Tutorial
WD3 - Custom Design
Top Down Schematic Driven Layout Flow
Author(s): Ken Chuang - Synopsys
Tutorial
User Presentation
TA1 - Physical Implementation
ICCII Speed Up Physical Implementation of a High-Performance Design
Author(s): Lu Yao - Amlogic
Presentation

Multiple Power Domain Design Planning Using IC Compiler II (Honorable Mention)
Author(s): Zach Hsu - MStar
Presentation
TD1 - AMS Simulation
SoC & IP System Verifiction Methodology with XA-VCS Cosim
Author(s): YC Lin - Novatek
Presentation
TD2 - AMS Simulation
Achieving High Library Quality for Design Robustness by SiliconSmart
Author(s): Ryan Chen - Himax
Presentation
TE1 - Prototyping
Rapid Digital Signal Camera Prototyping System with Synopsys Auto-Partition Solution
Author(s): Robinson Mei - iCatch
Presentation

Real-Time 4K 120Hz Video Display SoC Prototyping System Using HAPS-80 and ProtoCompiler
Author(s): Kelvin Huang - Himax
Presentation
WA2 - Implementation
Improved Predictability and Quality of Results with Design Compiler Graphical (Award Winner)
Author(s): Kazuyuki Irie, Eric Liao - GUC
Presentation

N20 ARM Midgard High Performance GPU Implementation - Preparing the Best Starting Point for Real Silicon
Author(s): Shuan Lin - MediaTek
Presentation
WA3 - Physical Implementation
Mali-T400 Series Large Flatten and Hierarchical Design Implementation Flow with IC Compiler II
Author(s): Jay Cho - Novatek; Jackie Wu - Synopsys
Presentation
WB3 - Test
Experience Sharing on In-System Self-Test Using DFTMAX LogicBIST and SpyGlass
Author(s): CN Ho, Karl Chang - GUC
Presentation

Hierarchical DFT on Hundreds Million Gate Design
Author(s): Gavin Hung - MediaTek
Presentation
WD2 - Custom Design
FinFET Solution and Layout Productivity in Laker
Author(s): Cathy Lin - Sunplus
Presentation
WD3 - Custom Design
LakerOA Adoption Challenge and Advantage
Author(s): Wallace Chen - Richtek
Presentation
SILICON VALLEY 2017 KEYNOTE

Dr. Peter Stone on “Learning and Multiagent Reasoning for Autonomous Robots”

HISTORICAL PROCEEDINGS

Contact the SNUG Operations team for proceedings prior to 2013

View All SNUG Proceedings
Contact Us

Platinum Sponsors:

ARM
GLOBALFOUNDRIES
SAMSUNG
GLOBALFOUNDRIES
Related Items