SNUG Taiwan 2015 Proceedings

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Complete Proceedings


Speeches
Industry Keynote
Everyday Genius - How Design Makes Technology Better
Author(s): Andrew Chang, Corporate Senior Vice President - MediaTek, Inc.

Five Must-Knows for the Semiconductor Industry in the Internet of Things
Author(s): Jui-Lin Yang, Deputy Program Director – Industrial Economics & Knowledge Center, Industrial Technology Research Institute

Flash Memory History and Phison
Author(s): K.S. Pua, Founder, Chairman, and CEO - PHISON Electronics Corp.

I.O.T. Foundry with Green DNA
Author(s): Bill Chuang, Marketing Director - United Microelectronics Corporation

Welcome and Synopsys Keynote
At the Heart of Electronics, Design Makes Everything Different
Author(s): Dr. Antun Domic, Executive Vice President and General Manager, Design Group - Synopsys

Welcome and Verification Direction Presentation
Synopsys Verification Direction - Rethinking SoC Verification
Author(s): Ken Nelsen, Vice President, Global Technical Services - Synopsys

User Papers and Presentations
TA1 - Implementation I
TA1.1 UPF Partitioning Challenges in DVFS Era
Author(s): Jian-Wei Lin, Hsiung-Kai Chen, Lan-Sin Liau - MediaTek
PaperPresentation

TA1.2 IC Compiler Multisource CTS - Practical Experience Sharing
Author(s): Yih-Chih Chou - GUC
PaperPresentation

TA3 - Verification Continuum
TA3.1 USB Test Suite - The Window to Successful Verification
Author(s): Vincent Huang - Realtek; Ming Yang , Suchir Gupta , Jaspreet Singh Gambhir - Synopsys
PaperPresentation

TA3.2 Divide and Conquer of MIPI CSI2 MAC and PHY Verification
Author(s): Allen Tsai, Pokai Chang, Wayne Wang - Mstar; Nitin Agarwa - Synopsys
PaperPresentation

TB1 - Implementation I
TB1.1 Quick Migrate to IC Compiler II
Author(s): Jack Lo, Hui-Shan Ho - Mstar
PaperPresentation

TB1.2 Differentiated ICC II Technologies for Handling Large SoC
Author(s): Xia Li , James Su - MediaTek
PaperPresentation

TB3 - Verification Continuum
TB3.1 UPF Modeling of Retention Register
Author(s): Shang-Wei Tu - MediaTek; Amol Herlekar , Tiger Hsu - Synopsys
PaperPresentation

TB3.2 Universal Low Power Verification of Multi-Apps SoC
Author(s): Hsiu-Hsiung Chen, Liao Sung De - Nuvoton; Vikram Malik , Joseph Huang , Tiger Hsu, Leo Chang - Synopsys
PaperPresentation

TB4 - Integrated AMS Solution
TB4.1 SiliconSmart Performance and FR Enhancement on Standard Cell
Author(s): Eric Chang - Maxchip
Presentation

TB4.2 Standard Cell and Mixed-Signal IP Characterization Using SiliconSmart
Author(s): Shih Ji Wang - Sunplus
Presentation

WA2 - Implementation II
WA2.2 Test Quality Improvement Using Advanced Fault Models
Author(s): Chintan Panchal - einfochips
PaperPresentation

WA3 - Verification Continuum 1
WA3.1 Automated Flow Using Formal Methodology to Reach Hundred Percent Line Coverage
Author(s): Tsungyu Tsai - MediaTek; Tom Lin, Alvin Chen - Synopsys
PaperPresentation

WA3.2 VC-Platform and VC-APPs integration - Multiple Power Domain Fanout Nets
Author(s): Chen Yu-Juei - MediaTek
PaperPresentation

WA3.3 New Methodology for Power Estimation in ASIC Early Stage - Siloti Power Estimation Flow
Author(s): Sheng Hong Wang, Tzung-Rung Jung - Novatek; Lance Liu - Synopsys
PaperPresentation

WB2 - Implementation II
WB2.1 Accelerating Manufacturing Compliance Using ICV In-Design Flow Within IC Compiler II for Emerging Technology Nodes
Author(s): Rachel Weng, Naresh Lakkamraju, Jingchun Han, Yi Dai - MediaTek
PaperPresentation

WB4 - Integrated AMS Solution
WB4.1 Circuit Design and Simulation Implementation in CDSE/SAE
Author(s): Jeff Huang - iCatchTek
Presentation

Publication Only
Publish Only
Automating UVM Testbench Generation and Code Management
Author(s): Naveed Mahmud, Shakerin Ahmed - Ulkasemi Private Limited
Publish Only

Tutorials
TA1 - Implementation I
TA1.4 IC Compiler's Latest Release (2014.09) Delivers Significant Performance Power Area Improvements and Faster Closure on Emerging and Established Nodes
Author(s): Don Hsueh - Synopsys
Tutorial

TA3 - Verification Continuum
TA3.3 Utilizing VIP Testsuites
Author(s): Nitin Agarwal- Synopsys
Tutorial

TA4 - Integrated AMS Solution
TA4.2 How Custom Designer Can Improve Your Circuit Design and Simulation Productivity
Author(s): Chihwei Chan - Synopsys
Tutorial

TA5 - Hybrid Prototyping
TA5.1 Multi-FPGA Prototyping of 1.5 Billion ASIC Gates
Author(s): Mick Posner - Synopsys
Tutorial

TA5.3 X-Ray Vision - High Visibility Multi-FPGA Debug for FPGA-Based Prototypes
Author(s): Peter Zhang - Synopsys
Tutorial

TA6 - Software Quality
TA6.1 Introduction to Software Quality and Security in the Emerging Internet of Things
Author(s): Yan Huang - Synopsys
Tutorial

TB1 - Implementation I
TB1.4 ARM Cortex-A53 Multi-Core Network Computing Reference Implementation on Samsung 14LPP FinFET Process
Author(s): Andy Potemski - Synopsys
Tutorial

TB2 - Implementation II
TB2.2 Large Scale Design STA - Hierarchical or Flat, Distributed or Single Machine - Which Way to Go for Timing Signoff? STA Tutorial
Author(s): Brad Lee - Synopsys
Tutorial

TB2.3 Design Compiler and Formality 2015.06 Update
Author(s): Peter Tseng - Synopsys
Tutorial

TB3 - Verification Continuum
TB3.3 Overview of Synopsys Memory VIP
Author(s): Jason Liu, Nitin Agarwal - Synopsys
Tutorial

TB4 - Integrated AMS Solution
TB4.4 Innovations in Fast and Accurate Transistor-level Simulation Using HSPICE, FineSim SPICE, and WaveView for Post Processing
Author(s): Cathy Chou - Synopsys
Tutorial

TB5 - Hybrid Prototyping
TB5.2 Power-Aware Architecture Design for Multicore SoCs
Author(s): Pat Sheridan - Synopsys
Tutorial

TB5.3 Fast IP Software Development & Integration with Virtual & FPGA-Based Prototyping - DesignWare Hybrid IP Prototyping Kits
Author(s): Jiff Kuo - Synopsys
Tutorial

WA2 - Implementation II
WA2.4 Meet Your Test Quality and Cost Goals on Schedule
Author(s): Mark Lin - Synopsys
Tutorial

WA3 - Verification Continuum 1
WA3.4 Accurate and 10x Speedup Power Consumption Analysis at Early Design Stage with Siloti/Verdi3/VC-Apps
Author(s): Rich Chang - Synopsys
Tutorial

WA4 - Integrated AMS Solution
WA4.3 CustomSim Updates for Circuit Simulation
Author(s): Titus Liang - Synopsys
Tutorial

WA5 - IP
WA5.1 Energy Harvesting, Sensors, and SoCs for the IoT Era
Author(s): Jamil Kawa - Synopsys
Tutorial

WB1 - Implementation I
WB1.1 IC Compiler II Marketing and R&D Update
Author(s): Sanjay Bali, Neeraj Kaul - Synopsys

WB1.2 IC Compiler II Technology Tutorial
Author(s): Derrick Lin - Synopsys
Tutorial

WB2 - Implementation II
WB2.3 PrimeRail - Using Advanced Rail Analysis in the In-Design IC Compiler Implementation Flow
Author(s): Nora Lin - Synopsys
Tutorial

WB4 - Integrated AMS Solution
WB4.3 Synopsys Custom Layout Integration Flow Overview
Author(s): Nathan Lee - Synopsys
Tutorial

WB5 - IP
WA5.1 Optimize DDR Memory Subsystems for Performance, Power, and Cost
Author(s): William Chen - Synopsys
Tutorial

WB6 - Verification Continuum II
WB6.1 Universal and Integrated Platform of Debug and Verification
Author(s): Rich Chang - Synopsys
Presentation

Panel Presentation
Panel Luncheon
An Ecosystem Panel Perspective on Successfully Designing with FinFET
Author(s):

TA2 - Implementation II
TA2.1 Design Compiler Graphical For High Performance Core Design
Author(s): MediaTek, ARM, Mstar, Synopsys

WA1 - Implementation I
WA1.2 IC Complier II - Accelerating Products to Market
Author(s): MediaTek, TSMC, Synopsys

Combo
TA4 - Integrated AMS Solution
TA4.1 TSMC FinFET reference flow using Synopsys Custom Designer and Laker
Author(s): Brian Yang - TSMC; Lucas Chen - Synopsys

WA1 - Implementation I
WA1.1 High-Performance, Energy Efficient Implementation of the ARM Cortex-A72 Processor Core in 16-nanometer FinFET Plus (16FF+) Process Technology Using Synopsys Galaxy Design Platform
Author(s): JC Yu - ARM; Jow Walston - Synopsys
Presentation

User Presentation
TA1 - Implementation I
TA1.3 An ICC II Approach for Timing Closure in Advanced Nodes
Author(s): James Su, Subhash Sharma - MediaTek
PaperPresentation

TA2 - Implementation II
TA2.2 Synthesis Strategies for DVFS Designs
Author(s): Lily Huang - MediaTek
Presentation

TA4 - Integrated AMS Solution
TA4.3 Experience Sharing of FineSim Tool Usage in Flash Design
Author(s): Arvin Huang - Powerchip
Presentation

TA5 - Hybrid Prototyping
TA5.2 Earliest SW/HW Co-Development for Complex SoCs Using ProtoCompiler Enabled FPGA Prototyping Platforms
Author(s): Tim Lai - Realtek
Presentation

TA6 - Software Quality
TA6.2 Introduction to Vulnerability Management
Author(s): James Chiang - LCNC
Presentation

TB1 - Implementation I
TB1.3 Boost Productivity Using ICC II - A Multimedia Block Case Study
Author(s): Encheng Liu - Realtek
Presentation

TB2 - Implementation II
TB2.1 PrimeTime Timing and Power ECO Practical Experiment Result
Author(s): Meng-Hsiu Tsai - GUC
Presentation

TB4 - Integrated AMS Solution
TB4.3 Timing Analysis of Self-Timed SRAM Designs by Using NanoTime for Memory with Dynamic Clock Simulation Feature
Author(s): CJ Dai - TSMC

TB5 - Hybrid Prototyping
TB5.1 Prototypes on High Speed Rails - When Schedule is the Priority
Author(s): Chunhsiang Peng - Sunplus
Presentation

WA2 - Implementation II
WA2.1 High Quality Transition Test with Synchronous OCC for Scan-Based Design
Author(s): CN Ho - GUC
Presentation

WA4 - Integrated AMS Solution
WA4.1 Run Time Improvement by Power Net RC Optimization with Automatic Power Net Identification Feature of CustomSim
Author(s): Gary Chan - TSMC

WA4.2 TMI Modeling for FinFET IC Simulation
Author(s): YC Liang - TSMC

WA5 - IP
WA5.2 DesignWare STAR Memory System Test and Repair Solution for Imagination's 16FF+ PowerVR Series 7 GPU
Author(s): Sumit Kansal - Imagination
Presentation

WB2 - Implementation II
WB2.2 Dynamic IR Analysis with RTL-VCD Flow at Earlier Stage
Author(s): Hsinhung Liu - Sunplus
Presentation

WB4 - Integrated AMS Solution
WB4.2 Accelerating Physical Design Flow in Laker with TCL Applications and Third Party Tool Integration
Author(s): Liang Wu - Himax

WB6 - Verification Continuum II
WB6.2 Best Practices for Linux Driver Development and RTL Behavior Analysis in PCIE Hybrid Emulation
Author(s): Ennis Ko - Mstar; Owen Chang - Synopsys
Presentation

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