SNUG Taiwan 2014 Proceedings

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Complete Proceedings


Speeches
Industry Keynote
Industry Opportunities in the OIP Era
Author(s): Mr. Suk Lee, Senior Director, TSMC

A Journey to Smart World
Author(s): Mr. Denny Liu, Special Assistant, Design Tech, MediaTek Inc.

Disruptive Trends - Surfing The Big Wave
Author(s): Dr. JJ Wu, Vice President, Strategic Marketing, UMC

Welcome - SNUG Technical Committee
SNUG Technical Committee
Author(s): Dr. Chi-Feng Wu, SNUG Taiwan Technical Committee Chairperson

Welcome and Industry Keynote
IP Driving Innovation: from Pillars to Platforms
Author(s): Sir Hossein Yassaie, CEO, Imagination Technologies

Welcome and Synopsys Keynote
Addressing Today's Increasing Design Complexity Through Innovation and Collaboration
Author(s): Dr. Paul Lo, Senior VP Synopsys Inc.

User Papers and Presentations
TA1: Physical Implementation
TA1.3 Concurrent Clock Tree OCV and Process Corner Variation Reduction (Best Paper Award)
Author(s): Chien-Pang Lu - MediaTek
PaperPresentation

TA2: Test
TA2.1 High Scan Compression for Pin-Limited Test by Using DFTMAX Ultra
Author(s): Max Wu - Realtek
PaperPresentation

TA4: RTL Verification and Debug
TA4.2 Missing Piece of Low Power Verification: UPF Code Coverage (Best Paper Award)
Author(s): Shang-Wei Tu - MediaTek, Tom Lin - Synopsys
PaperPresentation

TB1: Physical Implementation
TB1.1 Leakage Power Optimization and Congestion Aware Feedthrough Methodology (Best Paper Award)
Author(s): Andrew Shen, Ryan Su - MediaTek
PaperPresentation

TB4: RTL Verification and Debug
TB4.1 Seamless Transition: Test Cases Reuse between PCIe and mPCIe
Author(s): Adrian Wen - MediaTek, Anunay Bajaj, Alvin Chen - Synopsys
PaperPresentation

TB4.2 Building A Robust Memory Controller Verification Environment
Author(s): Sung-Yu Chen - Realtek, Ming Yang, Tom Lin - Synopsys
PaperPresentation

WA5: VC Apps
WA5.1 An Automated Multi-Rail Macro Extraction Flow by Using VC Apps
Author(s): Yu-Juei Chen, Will Lin, Shang-Wei Tu - MediaTek, Paul Huang - Synopsys
PaperPresentation

Tutorials
TA1: Physical Implementation
TA1.1 IC Compiler II and the Power of 10x: A Product Walk-Through
Author(s): Sanjay Bali, Henry Sheng - Synopsys

TA2: Test
TA2.3 Low DPPM and Low Cost Testing for All Process Nodes and FinFETs
Author(s): Mark Lin - Synopsys
Tutorial

TA4: RTL Verification and Debug
TA4.3 UVM Verification Using Verification IP
Author(s): Alvin Chen - Synopsys
Tutorial

TB1: Physical Implementation
TB1.3 Emerging Node Design with IC Compiler
Author(s): George Chou - Synopsys
Tutorial

TB2: STA
TB2.2 PrimeTime 2014.06 Highlights
Author(s): George Wang - Synopsys
Tutorial

TB3: Circuit Simulation
TB3.3 HSPICE, FineSim, CustomSim Solutions for Tomorrow's Challenge
Author(s): Eric Tsai - Synopsys
Tutorial

TB4: RTL Verification and Debug
TB4.3 Verification Closure Flow
Author(s): Tom Lin - Synopsys
Tutorial

WA1: Physical Implementation
WA1.2 Low-Power Design Implementation
Author(s): Jackie Wu - Synopsys
Tutorial

WA2: Synthesis
WA2.2 Design Compiler: What’s New and Roadmap
Author(s): Wayne Wang - Synopsys
Tutorial

WA3: System and IP
WA3.2 Optimizing DDR Memory Efficiency with the DesignWare Enhanced Universal Memory Controller
Author(s): Patrick Sheridan - Synopsys
Tutorial

WA5: VC Apps
WA5.3 Taking Debug Productivity to the Next Level with Your Own VC Apps
Author(s): Rich Chang - Synopsys
Tutorial

WB1: Physical Implementation
WB1.1 Latest Advances in PrimeRail In-Design Vector Free Rail Analysis
Author(s): Jack Ting - Synopsys
Tutorial

WB1.3 Using Lynx Design System Automation to Accelerate SoC Design Processes – Design QoR Analysis, Custom Design Correlation, IP Validation & Release
Author(s): Andy Potemski - Synopsys
Tutorial

WB3: IP and Ecosystem
WB3.2 IP Prototyping Kit
Author(s): Allen Chang - Synopsys

WB4: Customer Design Using Laker
WB4.2 iPDK Development and Validation Methodology
Author(s): GC Yi - Synopsys
Tutorial

WB4.3 Introduction of Galaxy Custom Router
Author(s): Hung-Shih Wang - Synopsys
Tutorial

WB4.4 In-Design EM/IR Checking in Laker
Author(s): Hsin-Po Wang - Synopsys
Tutorial

WB5: Emulation and FPGA-Base Prototyping
WB5.3 Imagination GPU Partition Experience Sharing Using Synopsys HAPS70 and Protocompiler
Author(s): Andy Jolley - Synopsys
Tutorial

Vision Session
Visionary Speech
Implementation Vision Speech
Author(s): Dr. Henry Sheng, Group Director, Synopsys

Panel Presentation
TB2: STA
TB2.1 PrimeTime SIG - Accelerating Design Closure with PrimeTime Advanced Technologies
Author(s): Yen-Pin Chen - TSMC, Ken Kao - MediaTek, ChengKai Huang - Ali, Tzong-Maw Tsai - Synopsys

Combo
TB3: Circuit Simulation
TB3.2 Eliminate DDR3 Timing Errors with HSPICE and SoC/SiP/PCB Co-Design
Author(s): Humair Mandavia - Zuken

WB3: IP and Ecosystem
WB3.1 SOC Designs in IoT Era - IP Perspective Presentation
Author(s): Dan Kochpatcharin - TSMC

WB3.3 UMC Design Enablements - Advanced Technology IP Solution
Author(s): T H Lin - UMC

User Presentation
TA1: Physical Implementation
TA1.2 Integrated Tool Flow Certification for N16FinFET Design
Author(s): Chiming Li - TSMC
Presentation

TA2: Test
TA2.2 Strategy of Scan Compression Solution (Honorable Mention)
Author(s): Chih-Nan Ho - GUC
Presentation

TA3: Circuit Simulation
TA3.1 XA-VCS Co-Simulation for Mixed-Signal Design Verification
Author(s): Veronica Tao - MediaTek
Presentation

TA3.2 CustomSim-XA/VCS Co-Simulation in Anpec
Author(s): Dennis Sheng - ANPEC
Presentation

TA3.3 TMI Enhancement in Advance Technology Modeling
Author(s): Fairy Peng - TSMC
Presentation

TA3.4 Memory Characterization by SiliconSmart
Author(s): Eric Chang - MaxChip
Presentation

TB1: Physical Implementation
TB1.2 Collaboration on Physical Verification
Author(s): Anderson Huang - UMC
Presentation

TB3: Circuit Simulation
TB3.1 System-Level PCB Simulation, Worse-Case Eye and Receiver EQ.
Author(s): York Wang - Quanta
Presentation

WA1: Physical Implementation
WA1.1 LowPower/High Core Utilization G6200 with TSMC 28nm Process
Author(s): FJ Huang - MediaTek
Presentation

WA2: Synthesis
WA2.1 Improving Interactive ECO Efficiency Using Formality Ultra
Author(s): David Lee - HGST, David Low, Richard Su - Synopsys
Presentation

WA3: System and IP
WA3.1 SoC Design Service with Virtual Platform
Author(s): Ken Chen - Faraday
Presentation

WA4: Custom Design Using Laker
WA4.1 Custom Schematic Editing and Simulation Environment of CD-SE
Author(s): Jeffrey Yang - Frescologic
Presentation

WA4.2 Create Parameterized Device for DAC by Laker UDD
Author(s): Queena Lin - Faraday
Presentation

WA4.3 Productive Flow for Analog Design and Layout
Author(s): Cha Wei Cheng - MXIC
Presentation

WA4.4 Laker TCL Application on Bumping Mask Design
Author(s): Chao Lung He - SPIL
Presentation

WA5: VC Apps
WA5.2 Use VC Apps to Analyze Paths Between IP Blocks (Honorable Mention)
Author(s): Adrian Hung - Faraday
Presentation

WB1: Physical Implementation
WB1.2 Rapid Technology Readiness with Plug-in of Lynx Design System
Author(s): Kevin KW Liu - UMC
Presentation

WB4: Customer Design Using Laker
WB4.1 Synopsys Custom Design Solution for TSMC FinFET Technology
Author(s): Jill Liu - TSMC
Presentation

WB5: Emulation and FPGA-Base Prototyping
WB5.1 Multicore System Validation Methodology on ZeBu
Author(s): Shu-Hsuan Chou - MediaTek

WB5.2 Emulation and Simulation Acceleration with ZeBu
Author(s): Yung Jen Chen - Realtek
Presentation