Share your experience using Synopsys tools and IP at the 2019 Synopsys Users Group (SNUG) in Taiwan. SNUG brings together Synopsys users, technologists and industry experts for your local technical conference devoted to the challenges of electronic design and verification.
As a published SNUG author, you will increase your visibility in the local design and worldwide Synopsys User communities. In addition to the professional recognition, you will be eligible for the SNUG Best Paper Award and prize (please check your company’s gift acceptance policy).
The call for papers is open November 29, 2018 – February 5, 2019. The SNUG Team will review the submitted proposals and notify authors about abstract acceptance by February 11, 2019.
We have a preliminary list of topics to get you started, but don’t let that limit your ideas or innovation in your submission:
- Advanced Technologies: <20nm, 3DIC, FinFET & Established Nodes: 28nm and above
- Characterization: Standard Cell, Memory, I/Os, Complex Cells
- Design Applications: Arm, Automotive, Graphics/GPUs, IP, Machine Learning, Processors
- Design Closure: Timing, Power, ECOs and Signoff: Physical Verification, Timing, Extraction
- Design-For-Test and Yield Analysis
- Digital Design Methodologies: High Performance, Low Power, Area Optimization, Machine Learning
- Digital Verification: Simulation, Debug, Coverage, Verification IP, Formal and Static
- Emulation and Prototyping, System Design, Hardware/Software Integration and Validation
- FPGA Design and Verification
- Full Custom Design Flows, Transistor and Analog/Mixed-Signal Verification
- Your own great idea