SNUG Singapore 2016 Proceedings

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Complete Proceedings


User Papers and Presentations
Implementation I
20nm Custom Digital Circuit Structured Layout Auto Route with IC Compiler (Best Paper - Honorable Mention)
Author(s):
Paper Presentation

Disruptive Techniques for Area Reduction in Hierarchical Chip (Best Paper - Honorable Mention)
Author(s): Rajasekhar Ravipati, Navienkumar RA, Huaqing Wu, Jingchun Han - MediaTek
Paper Presentation

ICC VA Aware Port Punching (2nd Place - Best Paper)
Author(s):
Paper Presentation

Placement Guide Methodology for Better Placement Performance in ICC (1st Place - Best Paper)
Author(s): Swetha Venugopal - Realtek
Paper Presentation

Implementation II
Advanced Design Methodologies - Automatic Feed-Through (FT) Compiler (1st Place - Best Paper)
Author(s): Prabhat Gupta, Arun Kumar, E Raveendra, Abhay Sharma - MediaTek
Paper Presentation

PFET Enabling Hook Up Scheme to Balance Between Peak Rampup Current, Rampup Time and PFET Transient FiSH Temperature (Best Paper - Honorable Mention)
Author(s):
Paper Presentation

SoC Physical Implementation Challenges Using Mixed ICC2 and ICC1 (Best Paper - Honorable Mention)
Author(s): Ajay Kumar Nandagiri, JackQian Liu, Yi Song Wang - MediaTek
Paper Presentation

Virtual Partition Flow for Rapid Design Convergence (2nd Place - Best Paper)
Author(s):
Paper Presentation

Implementation III
At-Speed, All-Around Hierarchical Signoff with PrimeTime HyperScale (Best Paper - Honorable Mention)
Author(s): Xi Lin, Avinash Swarna, Kunkun Zhang - MediaTek
Paper Presentation

Breaking into the FDSOI Realm: Design Methodologies that Help Designers Succeed in GLOBALFOUNDRIES 22FDx Technology (Best Paper - Honorable Mention)
Author(s): Elisha Prashanth Sagar Nandavaram, Tze Haw Liew - GLOBALFOUNDRIES
Paper Presentation

Grid-Based Logic Replication for High-Speed Scan SLOS Timing Convergence (1st Place - Best Paper)
Author(s):
Paper Presentation

Power Related ATE Fails During Transition Test: A Case Study (2nd Place - Best Paper)
Author(s):
Paper Presentation

Verification
Advanced SoC Verification with Software Controlled Verification IP (Best Paper – Honorable Mention)
Author(s):
Paper Presentation

Complementing UVM Simulation with Formal Verification to Reduce Verification Cycle and Increase Verification Quality (2nd Place - Best Paper)
Author(s):
Paper Presentation

Is Gate Level Simulation Still Relevant in Verification Cycle? (Best Paper - Honorable Mention)
Author(s):
Paper Presentation

System-Level Performance Verification of Multi-Core SoC (1st Place - Best Paper)
Author(s):
Paper Presentation

Publication Only
A Novel Method to AutoFix Timing DRC for Rapid Design Convergence
Author(s): Chin Leong Lou, Chee Ying Ong - Chipglobe; Kim Wee Ng - Infineon
Publish Only

Advanced Leakage-Recovery Methodology in DMSA Environment
Author(s):
Publish Only

An ICV Runset Flow to Resolve Incorrect Capacitance Extraction in the SKIP_CELLS Extraction Methodology in StarRC
Author(s):
Publish Only

Efficiency and Agile Improvement in APR Using Hierarchical Flow
Author(s):
Publish Only

Maximize Test Coverage of a USB3 Subsystem
Author(s):
Publish Only

Novel Solution to Insert Scan in Complex Power Domains Design Block
Author(s):
Publish Only

Scan Flop Bypass Technique for Quick Convergence of Congested Design
Author(s):
Publish Only

Strategic Approach to Debug Watchdog, Exceptions and Stack Corruption
Author(s):
Publish Only

Testing DDR2/3 PHY in a SoC: A Case Study
Author(s):
Publish Only

Timing Closure with Automated Physically-Aware Timing ECO Flow
Author(s):
Publish Only

Virtual Channel Buffers for Realistic Early Physical Design Implementation
Author(s):
Publish Only

Tutorials
Implementation I
Accelerating Analog Verification - Simulation Analysis Environment
Author(s): Jiang Xi, Then Choo Kiong - Synopsys
Tutorial

Emerging Node Design with IC Compiler II / IC Validator
Author(s): Lam Lup Meng - Synopsys
Tutorial

Galaxy RTL: Design Compiler Family 2016.03 Update and Best Practices for Faster Runtime on Large Designs
Author(s): Manjunatha Visweswaraiah - Synopsys
Tutorial

Implementation II
Floorplanning Large Blocks Using IC Compiler II
Author(s): Yeong Kig Ling - Synopsys
Tutorial

IC Compiler II Delivers 10-20% Better Performance Power Area (PPA) on Advanced Designs
Author(s): Jayalal Vijayan - Synopsys
Tutorial

Implementation III
Address Testability Issues Early with SpyGlass DFT ADV
Author(s): Eric Lim - Synopsys
Tutorial

PrimeTime ECO Tutorial
Author(s): Gauri Sankar Malla - Synopsys
Tutorial

SpyGlass RTL Signoff - Static Verification Solution
Author(s): Vikas Kamboj - Synopsys
Tutorial

Verification
Achieving Higher Performance and Productivity with Native Integration of Simulation Flows
Author(s): Narendra Korlepara - Synopsys
Tutorial

Essential Ingredients of Formal Verification
Author(s): Neelabja Dutta - Synopsys
Tutorial

Key Techniques to Speed-Up Debug and Verification Closure – Recent Innovations in Verdi
Author(s): Tilak Chand Meka - Synopsys
Tutorial
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