SNUG Silicon Valley 2019 – IP Track

March 21, 2019
8 a.m. to 6:30 p.m.
Santa Clara Convention Center

Synopsys customers are invited to register for the IP track at SNUG Silicon Valley. The IP track, consisting of five technical tutorials, is focused on how you can easily integrate silicon-proven IP into your SoCs with less risk across a wide range of applications. Also, don’t miss other IP related sessions.



IP Track

 Building Secure Media Processors for Connected Homes using OTP NVM 

Jingliang Li, Synaptics | March 21, 10:45 a.m. – 11:30 a.m.

The connected home market requires high-performance, power-efficient processors to enable rich multimedia, seamless connectivity, and customized experiences on entertainment devices. A robust security engine is integral to such a system to ensure secure boot, video watermarking, and digital rights management (DRM) of premium content for TVs, set-top boxes, streaming, and gaming applications. Delivering immersive entertainment regardless of source requires secure storage of encryption keys, configuration, and version control information. In this presentation, Synaptics will describe their use of DesignWare OTP NVM to develop single-chip media processors with secure DRM for the connected home entertainment market.

Enabling 400G Hyperscale Data Centers with 56G Ethernet PHY IP

Rita Horner, Synopsys | March 21, 11:30 a.m. – 12:15 p.m.

The growth of data traffic for achieving performance-intensive tasks is driving the need for new data center architectures, Ethernet PHY IP and interconnects. Hyperscale data centers are shifting to faster, flatter, and more scalable network architectures. High-speed Ethernet solutions are transitioning to the PAM-4 modulation scheme, allowing high bandwidth and long reaches. 400G Ethernet interconnects are based on length requirements, density, form factor, and power consumption. This presentation details the new modulation schemes and Ethernet PHY IP architecture that can help you meet your design requirements for 400G+ hyperscale data center SoCs.

Using IP for LPDDR5/4/4X Connectivity and Memory Performance Optimization

Graham Allan, Synopsys | March 21, 1:45 p.m. – 2:30 p.m.

The JEDEC LPDDR5/4/4X memory standards primarily target mobile applications, providing high bandwidth memory access and numerous low-power states for power savings during idle time. Unlike DDR5/4/3, each independent channel is 16 bits wide and applications such as digital home/office, laptops, SSDs, AI, etc. typically connect to these memories in unintended ways, such as operating two 16-bit channels in lock-step. This presentation explains the different ways designers can connect to LPDDR5/4/4X SDRAMs and outlines the characteristics of each configuration including signal integrity trade-offs.

Implementing Monocular Visual SLAM for Augmented Reality in Low-Power Embedded Vision Systems

Gordon Cooper, Synopsys | March 21, 2:30 p.m. – 3:15 p.m.

Simultaneous localization and mapping (SLAM) is a deep learning technique that gathers visual data from the physical world to create 3D maps of the environment. Monocular visual SLAM relies on a single camera, like the one in mobile phones. SLAM executes computationally intensive tasks, such as feature extraction to identify landmarks, feature matching to determine the changing position of the camera, and loop detection and closure to estimate camera motion. Implementing these tasks on low-power devices like mobile phones requires computationally efficient and memory optimized solutions to reduce power consumption while keeping performance and latency at target levels. This presentation will explain the challenges augmented reality (AR) designers face when implementing SLAM in AR applications, offer solutions to reduce system power consumption, and provide a case study that describes how to combine deep learning and evolving SLAM techniques in low-power systems.

Accelerate Your Move to 32GT/s PCI Express 5.0 Designs

Gary Ruggles, Synopsys I March 21, 3:30 p.m. – 4:15 p.m. 

The PCI Express® 5.0 specification offers a fast interconnect technology for high-end computing and emerging artificial intelligence applications. However, moving to PCIe® 5.0 design requires designers to consider and overcome several key challenges including managing datapath width, timing closure, signal integrity, and complex packaging issues. In addition, a close collaboration between system designers, SoC designers, and layout designers becomes important. Attend this presentation to find out how to accelerate your move to 32GT/s PCIe® 5.0 designs using proven IP while managing your evolving design requirements.


AI Track

Enabling AI with IP  

Ron Lowman, Synopsys I March 20, 11:00 a.m. – 11:45 a.m. 

The progress of Artificial Intelligence innovations has accelerated, driving new chipset architectures targeted at embedded vision, autonomous driving, industrial automation, consumer entertainment, agriculture, and more. When planning the architecture of an embedded vision chip for AI applications, designers generally start with the processor and leave the interfaces (Ethernet, MIPI, CCIX, PCIe) for later in the process. However, the processors access to real-time data, memory, additional processing capabilities, or the cloud is critical to the performance of the SoC and the AI system as a whole. This presentation will review current market trends that are driving the need for bandwidth in several different applications. It will provide case studies of example AI chipsets for with a particular focus on inference data rate trends in different applications.


Test Track

Test and Repair for SoC Memories and Hierarchical Test for AMS & PHY IP

Yervant Zorian, Synopsys I March 20, 4:45 p.m. – 5:15 p.m. 

Memory Test and Repair @ 7nm and smaller technologies present new and unique challenges to SoC and DFT designers. With growing process variation and complexity, SoC designers need to overcome new memory fault types (specific to FinFET) to offer high test coverage while satisfying performance and reliability needs specific to new applications like Artificial Intelligence, Machine Learning and Automotive. This tutorial will introduce the next generation of STAR Memory System (SMS), Synopsys’ memory test and repair solution including details of the recently announced support for embedded MRAM (eMRAM) technology. The speaker will also discuss the DesignWare STAR Hierarchical System (SHS), a hierarchical test and diagnostics solution for all analog/mixed signal IP/cores on your SoC. The tutorial will cover test, repair, diagnostics as well as in-field self-test capabilities with examples of successful customer case studies.


Automotive Track

Enabling Automotive - Quality Embedded Memories: Design and Test Enhancements

Frank Cano, Texas Instruments I March 20, 2:00 p.m. – 2:45 p.m.

Automotive applications pose stringent constraints on SoCs to support very low failure/FIT rates, very high quality of ~0 DPPM (defective parts per million), and long operational lifetimes withstanding a wide range of temperatures (-40C to 125C/150C). With increasing embedded memory content in recent automotive SoCs, a 1 DPPM requirement at SoC level translates to a 1 DPPB requirement at the embedded memory component level from a statistical perspective. Addressing this quality challenge to meet the needed ISO 26262 ASIL levels requires a holistic approach to the design and test of memories in 16nm and below technology nodes by ensuring that the design is tested in margin. In this paper, we present joint case-studies between Texas Instruments and Synopsys on techniques that were implemented in 16FFC embedded memories across IP design margin analysis, IP design enhancements for test quality improvement, testchip robustness improvement, and SoC design and test/screen improvements, to enable high automotive quality from the overall system perspective.

The Marriage of AI and Safety in Automotive SoCs

Fergus Casey, Synopsys I March 20, 2:45 p.m. – 3:30 p.m.  

As the automotive industry looks beyond Level 2 (Driver Assist) designs, the race is on to deliver high-performance safety-critical autonomous vehicle components powered by the latest AI technology. AI techniques can provide increased accuracy for object and pedestrian detection, but these designs must still meet the ISO 26262 standards most stringent level of functional safety and fault coverage. In this presentation, autonomous driving use-cases will be analyzed emphasizing the need for the inseparable union of AI and safety. From architecture through to tape-out, this session will provide an overview of the design, verification, and safety methodologies required for SoC safety certification. We will discuss how Synopsys achieves this marriage without significant impact on performance, power, or area compared to non-ASIL Ready processors.