DDR4 or HBM2 High Bandwidth Memory: How to Choose Now
Graham Allan, Synopsys | March 23rd, 10:30 a.m. to 11:15 a.m.
High Bandwidth Memory (HBM) is now in volume production in high-end consumer graphics cards. The second version of the standard, HBM2, is set to enable the next generation of High Performance Computing (HPC) and networking chips. While DDR4 is a fast and high capacity DRAM interface offering 200Gbit/s per DIMM, HBM2 delivers very high memory bandwidth up to 2 terabits per second, per die stack, with low energy per bit, and low PCB area. HBM2 uses 2.5D interposer technology and 3D stacking to make thousands of connections between the CPU SoC and the HBM2 device but has many new challenges that were not present in DDR DRAMs. This session focuses on the key points to consider when deciding between DDR4 and HBM2, and focuses on the new requirements when using HBM2 like system-level architecture, physical design, and test.
Design Considerations for Integrating PCI Express 4.0 and CCIX
Richard Solomon, Synopsys | March 23rd, 11:15 a.m. to 12:00 p.m.
With the recent Draft 0.7 release of the PCI Express® (PCIe) 4.0 Base Specification, many SoC designers and architects are kicking their 16GT/s design efforts into high gear. This session explains the functionality and design impacts of key new features introduced with this draft of the specification. In addition, we will discuss the announced Cache Coherent Interconnect for Accelerators (CCIX) specification. We will discuss the implementation and design impacts of utilizing CCIX’s Extended Speed Modes (ESM) in conjunction with PCI Express.
Building Security in Your SoC with a Hardware Root of Trust Secure Module
Andrew Elias, Synopsys | March 23rd, 1:30 p.m. to 2:20 p.m.
Attacks on connected devices has increased dramatically in the last couple of years. Security is critical at all levels -- during operation, at power up, power down -- and it all starts with the SoC. Building an isolated secure environment within the SoC protects the device from malicious attacks. This session discusses how you can implement a trusted environment with a Root of Trust secure module consisting of HW, firmware, and tools that enable you to develop a unique identity within your SoC that can’t be tampered with. It will describe how you can maintain the integrity of the SoC software through the device operation and life-cycle, as well as securely debug and update the software in the field.
USB Type-C Connects Them All
Morten Christiansen, Synopsys | March 23rd, 3:30 p.m. to 4:15 p.m.
USB Type-C is widely adopted. Most new laptops, tablet, mobile phones, and devices have converted to USB Type-C. Now that USB Type-C is becoming ubiquitous, SoC designers must understand how to design for USB Type-C and satisfy time-to-market, size, power, and cost requirements. This tutorial explores technical requirements and solutions for USB Type-C host, device and Dual Role Port, DisplayPort Alternate Mode, HDMI Alternate Mode, USB Type-C chargers with and without Power Delivery, USB Type-C Authentication, and the new USB Audio Device Class 3.0 for mobile products without legacy 3.5mm analog audio jack. Of special interest for SoC designers is HW and SW partitioning challenges and proposed solutions.
IP Lunch and Learn: Under The Hood: What It Takes to Meet Automotive Compliance
Navraj Nandra - Synopsys | 12:00 p.m. to 1:00 p.m.
Meeting stringent automotive compliance for next-generation ADAS and MCU system-on-chips requires knowledge and experience at all levels. At the system level, designers need to ensure that their products meet automotive standards, such as ISO 26262 functional safety, AEC-Q100 reliability testing, and TS 16949 quality management. Furthermore, these chips are being developed in the latest FinFET technologies due to the significant processing required to interpret, recognize, and react based on embedded vision processors. As a result, the IP provider must have the expertise to assess the impact of aging/reliability such as HTOL, EM, TDDB, and NBTI on the IP, together with compliance requirements such as the addition of functional safety diagnostics. This presentation will go under the hood to provide insights into the technical specifications and design decisions needed to develop automotive grade IP, which helps accelerate compliance of automotive systems for semiconductors, Tier 1s, and OEMs.
Integrating USB 3.0 Controller and Intel USB 2.0 and HSIC PHYs
Jihad Abbas, Nader Haddad, Intel & Shivakumar Chonnad, Synopsys | March 23rd, 2:20 p.m. to 3:10 p.m.
This paper discusses the integration of Synopsys USB3.0 controller IP and Intel USB2.0 and HSIC PHY’s. It describes the steps followed, from the initial reviews to the final handoff. The assumptions made, the validation and the resolution of all the issues that were encountered are discussed. The end result, a test chip developed by Intel and validated for interoperability by Synopsys, is presented.
Advanced Memory Test and Repair with SMS and Hierarchical Test and Diagnosis from IPs to SoC with SHS
Yervant Zorian, Synopsys | March 23rd, 1:30 p.m. to 2:15 p.m.
Comprehensive SoC Test, Diagnostics, and Repair present multi-dimensional set of challenges to chip designers. With growing IP, device and process complexity, SoC designers need to overcome increased test cost, handle new fault types (specific to FinFET), while still satisfying needs specific to their applications, like IoT, mobile, or automotive. This tutorial will discuss the DesignWare® STAR Memory System (SMS), Synopsys’ memory test and repair solution, as well as the DesignWare STAR Hierarchical System (SHS), the hierarchical test and diagnostics solution for all IP/cores on your SoC, including interface IP, analog/mixed signal IP and digital logic blocks. The tutorial will cover the design flow, manufacturing test and repair, and in-field self-test and reliability strategies, capabilities and use models.
SoC Test Solutions for Safety Critical Automotive Designs
Yervant Zorian, Adam Cron, Synopsys | March 22nd, 3:45 p.m. to 4:30 p.m.
Automotive semiconductors require a focus on functional safety, reliability, and quality along with high coverage test solutions. These solutions must cover development, production, Power On Self Test (POST) and in-system test requirements. Large SoCs with memory, CPUs, analog, and digital blocks, large bus structures, and both analog and digital IP require all of these blocks to be thoroughly tested. This tutorial will discuss how to develop an effective test strategy and build a robust test solution for automotive SoCs.
Meeting IP Requirements of ADAS Automotive SoCs
Ron DiGuiseppe, Synopsys | March 22nd, 4:30 p.m. to 5:15 p.m.
As the automotive semiconductor industry develops SoCs for use in safety critical systems, they require IP that meets the stringent automotive requirements of ISO 26262 Functional Safety. This session will review best practices for the development and certification of ASIL Ready IP according to ISO 26262. The session will review how ISO 26262 requirements impact IP and summarize the IP deliverables provided by Synopsys for ADAS applications. In addition, the requirements for automotive AEC Q100 reliability and automotive quality according to TS 16949 will be reviewed. The session will highlight the IP required for high performance ADAS SoCs built on FinFET processes, and how IP providers can help automotive SoC suppliers obtain a fast path to volume production.