SNUG Silicon Valley 2016 Proceedings

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Complete Proceedings


Speeches
Keynote
What Else Besides FinFET?
Author(s): Chenming Hu - Professor at UC Berkeley
Video

Welcome and Keynote
Smart Everything: This Is Happening
Author(s): Aart de Geus, Chairman and co-CEO, Synopsys
Video

User Papers and Presentations
TA-01 Design Compiler Update and Runtime Best Practices Plus Verilog Versus VHDL
Language Wars in the 21st Century: Verilog Versus VHDL – Revisited
Author(s): Steve Golson - Trilobyte Systems; Leah Clark
Paper Presentation

TA-02 Advanced Floorplanning Methodology
Reusing Macro Placements with IC Compiler II
Author(s): Sameer Pujari - Advanced Micro Devices
Presentation

TA-05 User Experiences: Improving Timing Analysis Flows
Methodology to Close Timing with Hundreds of Multi-Mode/Multi-Corner Scenarios (3rd Place - Best Presentation)
Author(s): Stella Matarrese, Amit Shaligram, Manish Kumar Karna, Soniya I. Hirani - STMicroelectronics
Paper Presentation

Think Outside the STA Box
Author(s): Johnie Au, Fu-Hing Ho - Xilinx
Paper Presentation

TA-06 UVM-Based Verification
Layering Protocols with Chained Sequencers (3rd Place - Best Paper, Technical Committee Award, 2nd Place - Best Presentation)
Author(s): Brian Hunter - Cavium
Paper Presentation

UVM Register Access Layer: Get Your Quirky On!
Author(s): Tim Corcoran - Willamette HDL
Paper Presentation

TA-08 Virtual Prototyping with Virtualizer and VDKs
High Level Performance Estimation on Virtual Prototypes Employing Timing Annotation
Author(s): Robert Kaye - ARM
Paper Presentation

Virtual Platform Methodology for Large Scale Pre-Silicon Software Development – A Qualcomm Success Story
Author(s): Avin Kannur, Rajiv Narayan - Qualcomm
Presentation

TA-09 Successful LPDDR3 IP Implementation and Security IP
Right to First-Pass Success: A Silicon Story of Using Synopsys LPDDR3 in an SoC - What Went Right
Author(s): Mohit Kumar, Chakrapal Kalwa - Broadcom
Paper Presentation

TA-10 Mixed-Signal Verification VCS AMS (CustomSim-VCS)
PageFlash Memory Verification: Co-Simulation Methodology for Early Debug and Extensive Coverage Based on VCS AMS (CustomSim-VCS)
Author(s): Enrico Castaldo - STMicroelectronics; Claudio Rallo - Synopsys
Paper Presentation Session Recording

UVM Based Functional Verification of SerDes PHY Using VCS AMS (CustomSim-VCS)
Author(s): Prashanth Gurunath - Xilinx
Paper Presentation Session Recording

TB-03 Test User Session
Diagnosis of Single and Multiple Timing Issues in Scan Chains
Author(s): Richard Illman - Dialog Semiconductor
Paper Presentation Session Recording

Hierarchical Implementation of the Sequential Compression (SeqPlus) Architecture to Achieve Concurrent Testing (Best Paper Award, Technical Committee Award Honorable Mention)
Author(s): Jonathon E. Colburn, Milind Sonawane, Bala Tarun Nelapatla – NVIDIA
Paper Presentation Session Recording

Minimizing ATPG Pattern Simulation Failures Using Timing Exceptions for Stuck at and Transition Fault Nodes
Author(s): Manish Kumar Karna, Stella Matarrese, Giuseppe Fornaciari, Paul Filion, Pramod Kumar Singh, Giampaolo Mezzadri - STMicroelectronics
Paper Presentation Session Recording

Reliable Silicon Qualification of Standard Cell and IPs Using Synopsys OCC
Author(s): Eric Picollet, Kapil Juneja, Rajesh Kumar Immadi, Balwant Singh - STMicroelectronics
Paper Presentation Session Recording

TB-05 User Experiences: Timing Closure & Constraint Management
Constraints Development and Timing Closure Benefits of Using PrimeTime Automatic MUX Clock Exclusivity Feature
Author(s): Stella Matarrese - STMicroelectronics
Paper Presentation

Useful Techniques to Avoid Timing Closure Challenges During IP Flattening of SoC STA
Author(s): Manish Kumar Karna, Stella Matarrese - STMicroelectronics
Paper Presentation

Writing Efficient Timing Constraints and Accelerating Timing Closure with PrimeTime
Author(s): Ramnath Swamy - ARM
Paper Presentation

TC-05 New Dimension to Explore the Design Space Using Body-Bias Scaling Capability
Body-Bias Scaling – New Dimension to Explore the Design Space Using Body-Bias Capability
Author(s): Ramya Srinivasan - GLOBALFOUNDRIES
Presentation

WA-01 System Verilog
SystemVerilog Assertions - Bindfiles & Best Known Practices for Simple SVA Usage (1st Place - Best Presentation)
Author(s): Clifford E. Cummings - Sunburst Design
Paper Presentation Session Recording

SystemVerilog Logic Specific Processes for Synthesis - Benefits and Proper Usage (2nd Place - Best Paper, Technical Committee Award)
Author(s): Clifford E. Cummings - Sunburst Design
Paper Presentation Session Recording

WA-02 Advanced Design Methodology
Efficient Hierarchical Design of Analog I/O Sub-Systems
Author(s):
Paper Presentation

WA-06 Signoff Physical Verification
A Correct by Construction and Fast Method of Physical Integration and Signoff for Test Chip
Author(s):
Paper Presentation

WA-07 UVM-Based Verification
A Generic UVM Agent with Fine-Grain Command-Line Configuration (Best Paper Award, Technical Committee Award Honorable Mention)
Author(s): Nikhil Kikkeri, Daniel Wei, Anirban Bhattarcharjee, Sumanth Gudlavalleti, Hui Shi, Sandra Shih - Oracle
Paper Presentation Session Recording

Automating Test Creation from a Microarchitecture Specification
Author(s): Subramoni Parameswaran, Ravi Ram - Xilinx
Session Recording

WA-08 VCS-MX Precompiled IP and Verification Using Synopsys VIPs
Taming the Mammoth Build Time in Next Generation Tegra SoC Using VCS-MX Precompiled IP Feature
Author(s): Debashis Biswas - NVIDIA
Paper Presentation

WA-10 Circuit Simulation
Memory Cell Characterization in HSPICE
Author(s): Raed Sabbah - Micron Technology
Paper Presentation Session Recording

WB-01 Design Analysis
Data Analysis for Chip Design
Author(s): Avishek Panigrahi - Google
Paper Presentation

WaveDrom: Rendering Beautiful Waveforms from Plain Text
Author(s): Jonah Probell, Aliaksei Chapyzhenka - Arteris
Paper Presentation Session Recording

WB-03 FDSOI ERA and Voltage Scaling Methodology
Entering FD-SOI Era – Ease of Design Combined with Tunable Performance/Power Optimization Using GLOBALFOUNDRIES 22FDx Technology (1st Place - Best Paper, Technical Committee Award)
Author(s): Tamer Ragheb, Stefan Block, Wolfgang Daub, Juergen Dirks, Farid Labib, Rainer Mann, Haritez Narisetty, Herbert Preuthen, Fulvio Pugliese, Richard Trihy - GLOBALFOUNDRIES
Paper Presentation

Multi-Voltage CCS Scaling Accuracy with the Galaxy Implementation Flow
Author(s): Tejas Shah - Marvell Semiconductor
Paper Presentation

WB-05 Improving Timing and Power with PrimeTime ECO Flows
Timing Closure with Automated Physically-Aware Timing ECO Flow
Author(s):
Paper Presentation

WB-07 Circuit Simulation
Architecting Your Way to Acceleration in UVM
Author(s): Paul Lungu, Dean Justus - Ciena
Paper Presentation Session Recording

Using Synopsys VC Formal Coverage Analyzer (FCA) for Code Coverage Improvement
Author(s): Yuri Tatarnikov, Khaled Labib - SK Hynix Memory Solutions
Paper Presentation Session Recording

WB-08 Analog Mixed-Signal and Low Power Static Verification
Hierarchical Low-Power Static Verification Methodology for an FPGA Design
Author(s):
Paper Presentation

Recommendations for Increasing Accuracy of Analog Mixed-Signal Simulations by Minimizing Interface Dependencies
Author(s): Karin Mehlqvist, Jianfeng Shi - Broadcom
Paper Presentation

WB-10 Custom Design Technology
Parallel DRC Clean-Up Using the Unified Digital and Custom Co-Design Flow with IC Compiler and Synopsys Custom Layout Tool
Author(s): Nadeem Eleyan, Jeremy Bailey, Curtis Richardson, Patrick Szabo - Qualcomm ; Kelly Burleson, Frank Gover - Synopsys
Paper Presentation

WC-01 Verifying Timing Exceptions, Compute Infrastructure for EDA tools
Containerize Your Chip Development Environment Using Docker
Author(s): Chris Drake - Google
Paper Presentation

Herding Cats: How to Verify Timing Exceptions in Configurable IP
Author(s): Scott Evans - Sonics, Inc., Russell Roan - Synopsys
Paper Presentation Session Recording

WC-03 ICV In-Design Methodology
Reducing TAT and Achieving Timing Compatibility by New Metal Fill Flow Using In-Design ICV
Author(s): K.K. Lin, Jungsu An, Jinsuk Kim, Nandyala Ravi, Shinmo Kang, Jaehong Park - Samsung
Paper Presentation

WC-04 Memory BIST Embedded Test, Repair & Diagnostics and Hierarchical Test Solution
Automated Memory BIST Insertion and Validation for SSD Controller-Based SoC
Author(s): Padma Nagaraja, Vaibhavi Sabharanjak, Sumanth Shantaram, Dinesh Kumar Tadepalli - SanDisk; Khachatur Armenyan - Synopsys
Paper Presentation

Publication Only
Bottom-Up Reusable Timing Constraints Development and Validation Methodology in Case of Multiplexed External Interfaces
Author(s): Samuel Intiso, Jonas Oxenholt, Jan Bengtsson
Paper

Clock Design Challenges in a Large, Low-Power, High-Speed Signal Processing Design
Author(s): Rishi Yadav, Nimit Nguansiri
Paper

Data Mining STA Reports
Author(s): Nikhil Dakwala
Paper

Hidden VCS Gems for Designers
Author(s): Dinesh Venkatachalam
Paper

Smart Module Replacement (SMR) Flow for Accelerated IP/SOC Time to Market
Author(s): Monika Sane, Ryan Mascarenhas
Paper

Thank you VGEN - Complex SoC Assertion Qualification Turnaround Time from Hours to Minutes
Author(s): Sreenu Yerabolu, Sachin Scaria
Paper

Tutorials
TA-01 Design Compiler Update and Runtime Best Practices Plus Verilog Versus VHDL
Galaxy RTL: Design Compiler Family 2016.03 Update and Best Practices for Faster Runtime on Large Designs
Author(s): Bob Wiegand - Synopsys
Tutorial

TA-02 Advanced Floorplanning Methodology
Floorplanning Large Blocks Using IC Compiler II
Author(s): Aparna Lokanathan - Synopsys
Tutorial Video

TA-03 Lowering DPPM, Testing Safety Critical Circuits, and Improving Diagnostics Accuracy
Diagnosing Defective Silicon with TetraMAX
Author(s): Masato Nakazato - Toshiba; Brian Archer - Synopsys
Tutorial Video

Lowering DPPM and Testing Safety-Critical Circuits with Synopsys Test Automation Tools
Author(s): Adam Cron - Synopsys
Video

TA-04 Improving Productivity with NanoTime and Library Compiler
Best Practices in Library Qualification for Signoff
Author(s): Shirley Lu - Synopsys
Tutorial

NanoTime Accuracy Improvements Using HSPICE and FineSim
Author(s): Ketan Zaveri, Kyung Min, Sahil Bargal, Dave Jefferson - Synopsys
Tutorial Video

TA-07 Static Analysis with Spyglass
Static Analysis with Spyglass
Author(s): Sean O'Donohue - Synopsys
Tutorial Video

TB-01 Advanced UPF-Based Flow
Advanced Synopsys UPF-Based Flow to Perform Implementation & Verification
Author(s): Viswanath K. Ramanathan, Amol Herlekar - Synopsys
Tutorial Video

TB-06 Higher Performance and Productivity with Native Integrations
Achieving Higher Performance and Productivity with Native Integration of Simulation Flows Using Verification Compiler Platform
Author(s): Kiran Maiya, Bernie DeLay - Synopsys
Tutorial Video

TB-08 Early System Level Power Analysis Using Platform Architect MCO
Applying UPF 3.0 for Early, System-Level Power Analysis of SoCs with Micron DDR Memories
Author(s): Bill Randolph - Micron; Patrick Sheridan - Synopsys
Tutorial

TB-10 Circuit Simulation, CustomSim and ESP-Verdi Debugging
CustomSim Updates for Circuit Simulation
Author(s): Rayson Yam - Synopsys
Tutorial

Debugging Equivalence Mismatches Using the ESP-Verdi Interface
Author(s): Dave Hedges - Synopsys
Tutorial

TC-01 Formality Low Power Verification & 2016 Update
Complete Low Power Verification and Formality 2016.03 Update
Author(s): Robert Hatt - Synopsys
Tutorial Video

TC-03 Addressing Testability Early and Yielding High Quality Chips Using Cell-Aware Technology
Address Testability Issues Early with SpyGlass DFT ADV
Author(s): Fadi Maamari - Synopsys
Tutorial Video

Three Applications of Cell-Aware Technologies for Yielding High Quality Chips in Advanced Process Nodes
Author(s): Chris Schuermyer, Brian Archer - Synopsys
Tutorial Video

TC-06 Speed Up Debug and Verification Closure Using Verdi
Key Techniques to Speed Up Debug and Verification Closure – Recent Innovations in Verdi
Author(s): Mansour Amirfathi - Synopsys
Tutorial Video

TC-08 FPGA Implementation with Synplify Premier
Accelerate Your FPGA Design Schedules with Synplify Premier
Author(s): Paul Owens, William Luis - Synopsys
Tutorial

TC-10 Custom Implementation
FinFET IP Design Using Synopsys Latest Innovation in Custom Tools
Author(s): Bob Lefferts - Synopsys
Tutorial Video

WA-02 Advanced Design Methodology
IC Compiler II 2016.03 Technologies to Meet Aggressive Performance, Power, and Area Goals
Author(s): Charles Hsiao - Synopsys
Tutorial Video

WA-10 Circuit Simulation
Circuit Simulators Update: HSPICE, FineSim SPICE, and Custom WaveView ADV for Signal Integrity, Analog Simulations, and Waveform Post-Processing
Author(s): Khaled Nikro - Synopsys
Tutorial Video

WB-02 Advanced Application Methodology with ARM® CPU and GPU
Best Practices for High-Performance, Energy Efficient Implementations of the Latest ARM Processors in 16-nanometer FinFET Plus (16FF+) Process Technology Using Synopsys Galaxy Design Platform
Author(s): Mike Montana - Synopsys
Tutorial Video

WB-05 Improving Timing and Power with PrimeTime ECO Flows
Next Generation Low Power ECO for Signoff
Author(s): Stephan Mahnke - Synopsys
Tutorial Video

WB-09 HAPS Integrated Solution
Accelerate Your Prototyping Productivity Leveraging HAPS Integrated Prototyping Solution
Author(s): William Luis, Ajay Jagtiani - Synopsys
Tutorial Video

Adapt, Port, and Integrate Quickly – Prototyping the Right Way
Author(s): Antonio Salazar - Synopsys
Tutorial Video

WB-10 Custom Design Technology
Learn About the Latest Innovations in Custom Design for Advance Nodes in this Technology Walk-Through by Synopsys R&D
Author(s): Fred Sendig, Dave Reed - Synopsys
Tutorial Video

WC-02 Advanced Application Methodology for High-Performance GPU and Emerging Nodes
Best Practices for a Performance and Area Focused Implementation of High-Performance GPUs Using Galaxy Design Platform
Author(s): Daniel Biset - Synopsys
Tutorial Video

Emerging Node Design with IC Compiler II
Author(s): Mindy Kao - Synopsys
Tutorial Video

WC-03 ICV In-Design Methodology
Managing Metal Fill and Its Impact on Your Design
Author(s): Ed Rosebloom - Synopsys
Tutorial

WC-04 Memory BIST Embedded Test, Repair & Diagnostics and Hierarchical Test Solution
Solving Application Specific SoC Test, Diagnostics, and Repair Challenges
Author(s): Yervant Zorian - Synopsys
Tutorial

WC-05 Effective Reporting and Analysis of Timing Results
Advanced Reporting with PrimeTime
Author(s): Vijay Govindarajan - Synopsys
Tutorial Video

WC-06 StarRC Solutions for Faster Performance and Design Efficiency
What’s New in StarRC: Advances for Improving Productivity and Efficiency
Author(s): Krishnakumar Sundaresan - Synopsys
Tutorial

WC-07 Formal Based Verification Signoff
Essential Ingredients of Formal Based Verification Signoff
Author(s): Sean Safarpour - Synopsys
Tutorial Video

WC-10 Simulation Analysis Environment (SAE)
Walk-Through of SAE: The New Simulation Analysis Environment in the Latest Release of HSPICE, FineSim, and CustomSim
Author(s): Geoffrey Ying, Jon Sanders - Synopsys
Tutorial Video

Panel Presentation
TB-04 Challenges and Solutions for Library Development and Characterization
Panel: Solving the Challenges of Library Development and Modeling for Signoff – Today and the Future
Author(s): Kishore Singhal, Arindam Chatterjee, Nanda Gopal, Deepak Sherlekar - Synopsys
Tutorial

User Presentation
TB-01 Advanced UPF-Based Flow
Evolution of Socionext’s UPF Multi-Voltage Design Flow
Author(s): Mahiro Hikita - Socionext
Presentation

TB-04 Challenges and Solutions for Library Development and Characterization
SiliconSmart Advanced Features and Best Practices
Author(s): Animesh Datta, Mengyun Zhang - Qualcomm; Ning Jin - GLOBALFOUNDRIES; Felipe Frantz, Suhas Subhaschandra - Synopsys
Presentation

WA-06 Signoff Physical Verification
Interactive Physical Verification Flows Within Synopsys Custom Design Tool
Author(s): Randy You - GSI Technology
Paper

WA-08 VCS-MX Precompiled IP and Verification Using Synopsys VIPs
Plug & Play: Speeding Up Protocol Verification by Utilizing Synopsys VIPs
Author(s): Kathy Zhang - Avago Technologies
Presentation

WA-09 SoC Prototyping with HAPS
FPGA Debug: Improving Debug Turnaround Time in High Speed Designs
Author(s):
Presentation

Techniques Used to Partition a Complex-SoC into Multi-HAPS-70 System
Author(s): Ramanan Sanjeevi Krishnan, Sivarama Prasad Valluri - NVIDIA
Presentation Video

WB-02 Advanced Application Methodology with ARM® CPU and GPU
Optimized Implementation of 3GHz+ ARM CPU Cores in FinFET Technologies
Author(s): Cyrus Afghahi - Broadcom
Presentation  

WC-03 ICV In-Design Methodology
Fast Forward with In-Design Pattern Matching and Custom Fixing Flows
Author(s): Karthik Krishnamoorthy, Fadi Batarseh - GLOBALFOUNDRIES
Presentation

WC-06 StarRC Solutions for Faster Performance and Design Efficiency
NVIDIA's Experience Achieving Increased Productivity Using StarRC in Custom Design Flows
Author(s): Sudhir Agarwal - NVIDIA
Presentation

WC-09 HAPS
Address TTM by Prototyping and Validating SoC Design Using HAPS-70 System
Author(s): Xin Zhao, Veena Ramamurthy - SanDisk
Presentation

Reduce Overall TAT and Increase System Performance of Prototype Using ProtoCompiler
Author(s): Subhra Bandyopadhyay - Cisco
Presentation

WC-10 Simulation Analysis Environment (SAE)
Improving Advanced-Node Design Productivity with Synopsys Environment for SPICE Simulation and Analysis
Author(s): YongKwan Kim - Samsung
Presentation
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