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| User Papers and Presentations |
| TA-01 Design Compiler Update and Runtime Best Practices Plus Verilog Versus VHDL |
Language Wars in the 21st Century: Verilog Versus VHDL – Revisited
Author(s): Steve Golson - Trilobyte Systems; Leah Clark
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| TA-02 Advanced Floorplanning Methodology |
Reusing Macro Placements with IC Compiler II
Author(s): Sameer Pujari - Advanced Micro Devices
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| TA-05 User Experiences: Improving Timing Analysis Flows |
Methodology to Close Timing with Hundreds of Multi-Mode/Multi-Corner Scenarios (3rd Place - Best Presentation)
Author(s): Stella Matarrese, Amit Shaligram, Manish Kumar Karna, Soniya I. Hirani - STMicroelectronics
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Think Outside the STA Box
Author(s): Johnie Au, Fu-Hing Ho - Xilinx
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| TA-06 UVM-Based Verification |
Layering Protocols with Chained Sequencers (3rd Place - Best Paper, Technical Committee Award, 2nd Place - Best Presentation)
Author(s): Brian Hunter - Cavium
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UVM Register Access Layer: Get Your Quirky On!
Author(s): Tim Corcoran - Willamette HDL
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| TA-08 Virtual Prototyping with Virtualizer and VDKs |
High Level Performance Estimation on Virtual Prototypes Employing Timing Annotation
Author(s): Robert Kaye - ARM
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Virtual Platform Methodology for Large Scale Pre-Silicon Software Development – A Qualcomm Success Story
Author(s): Avin Kannur, Rajiv Narayan - Qualcomm
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| TA-09 Successful LPDDR3 IP Implementation and Security IP |
Right to First-Pass Success: A Silicon Story of Using Synopsys LPDDR3 in an SoC - What Went Right
Author(s): Mohit Kumar, Chakrapal Kalwa - Broadcom
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| TA-10 Mixed-Signal Verification VCS AMS (CustomSim-VCS) |
PageFlash Memory Verification: Co-Simulation Methodology for Early Debug and Extensive Coverage Based on VCS AMS (CustomSim-VCS)
Author(s): Enrico Castaldo - STMicroelectronics; Claudio Rallo - Synopsys
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UVM Based Functional Verification of SerDes PHY Using VCS AMS (CustomSim-VCS)
Author(s): Prashanth Gurunath - Xilinx
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| TB-03 Test User Session |
Diagnosis of Single and Multiple Timing Issues in Scan Chains
Author(s): Richard Illman - Dialog Semiconductor
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Hierarchical Implementation of the Sequential Compression (SeqPlus) Architecture to Achieve Concurrent Testing (Best Paper Award, Technical Committee Award Honorable Mention)
Author(s): Jonathon E. Colburn, Milind Sonawane, Bala Tarun Nelapatla – NVIDIA
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Minimizing ATPG Pattern Simulation Failures Using Timing Exceptions for Stuck at and Transition Fault Nodes
Author(s): Manish Kumar Karna, Stella Matarrese, Giuseppe Fornaciari, Paul Filion, Pramod Kumar Singh, Giampaolo Mezzadri - STMicroelectronics
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Reliable Silicon Qualification of Standard Cell and IPs Using Synopsys OCC
Author(s): Eric Picollet, Kapil Juneja, Rajesh Kumar Immadi, Balwant Singh - STMicroelectronics
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| TB-05 User Experiences: Timing Closure & Constraint Management |
Constraints Development and Timing Closure Benefits of Using PrimeTime Automatic MUX Clock Exclusivity Feature
Author(s): Stella Matarrese - STMicroelectronics
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Useful Techniques to Avoid Timing Closure Challenges During IP Flattening of SoC STA
Author(s): Manish Kumar Karna, Stella Matarrese - STMicroelectronics
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Writing Efficient Timing Constraints and Accelerating Timing Closure with PrimeTime
Author(s): Ramnath Swamy - ARM
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| TC-05 New Dimension to Explore the Design Space Using Body-Bias Scaling Capability |
Body-Bias Scaling – New Dimension to Explore the Design Space Using Body-Bias Capability
Author(s): Ramya Srinivasan - GLOBALFOUNDRIES
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| WA-01 System Verilog |
SystemVerilog Assertions - Bindfiles & Best Known Practices for Simple SVA Usage (1st Place - Best Presentation)
Author(s): Clifford E. Cummings - Sunburst Design
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SystemVerilog Logic Specific Processes for Synthesis - Benefits and Proper Usage (2nd Place - Best Paper, Technical Committee Award)
Author(s): Clifford E. Cummings - Sunburst Design
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| WA-02 Advanced Design Methodology |
Efficient Hierarchical Design of Analog I/O Sub-Systems
Author(s):
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| WA-06 Signoff Physical Verification |
A Correct by Construction and Fast Method of Physical Integration and Signoff for Test Chip
Author(s):
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| WA-07 UVM-Based Verification |
A Generic UVM Agent with Fine-Grain Command-Line Configuration (Best Paper Award, Technical Committee Award Honorable Mention)
Author(s): Nikhil Kikkeri, Daniel Wei, Anirban Bhattarcharjee, Sumanth Gudlavalleti, Hui Shi, Sandra Shih - Oracle
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Automating Test Creation from a Microarchitecture Specification
Author(s): Subramoni Parameswaran, Ravi Ram - Xilinx
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| WA-08 VCS-MX Precompiled IP and Verification Using Synopsys VIPs |
Taming the Mammoth Build Time in Next Generation Tegra SoC Using VCS-MX Precompiled IP Feature
Author(s): Debashis Biswas - NVIDIA
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| WA-10 Circuit Simulation |
Memory Cell Characterization in HSPICE
Author(s): Raed Sabbah - Micron Technology
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| WB-01 Design Analysis |
Data Analysis for Chip Design
Author(s): Avishek Panigrahi - Google
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WaveDrom: Rendering Beautiful Waveforms from Plain Text
Author(s): Jonah Probell, Aliaksei Chapyzhenka - Arteris
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| WB-03 FDSOI ERA and Voltage Scaling Methodology |
Entering FD-SOI Era – Ease of Design Combined with Tunable Performance/Power Optimization Using GLOBALFOUNDRIES 22FDx Technology (1st Place - Best Paper, Technical Committee Award)
Author(s): Tamer Ragheb, Stefan Block, Wolfgang Daub, Juergen Dirks, Farid Labib, Rainer Mann, Haritez Narisetty, Herbert Preuthen, Fulvio Pugliese, Richard Trihy - GLOBALFOUNDRIES
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Multi-Voltage CCS Scaling Accuracy with the Galaxy Implementation Flow
Author(s): Tejas Shah - Marvell Semiconductor
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| WB-05 Improving Timing and Power with PrimeTime ECO Flows |
Timing Closure with Automated Physically-Aware Timing ECO Flow
Author(s):
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| WB-07 Circuit Simulation |
Architecting Your Way to Acceleration in UVM
Author(s): Paul Lungu, Dean Justus - Ciena
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Using Synopsys VC Formal Coverage Analyzer (FCA) for Code Coverage Improvement
Author(s): Yuri Tatarnikov, Khaled Labib - SK Hynix Memory Solutions
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| WB-08 Analog Mixed-Signal and Low Power Static Verification |
Hierarchical Low-Power Static Verification Methodology for an FPGA Design
Author(s):
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Recommendations for Increasing Accuracy of Analog Mixed-Signal Simulations by Minimizing Interface Dependencies
Author(s): Karin Mehlqvist, Jianfeng Shi - Broadcom
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| WB-10 Custom Design Technology |
Parallel DRC Clean-Up Using the Unified Digital and Custom Co-Design Flow with IC Compiler and Synopsys Custom Layout Tool
Author(s): Nadeem Eleyan, Jeremy Bailey, Curtis Richardson, Patrick Szabo - Qualcomm ; Kelly Burleson, Frank Gover - Synopsys
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| WC-01 Verifying Timing Exceptions, Compute Infrastructure for EDA tools |
Containerize Your Chip Development Environment Using Docker
Author(s): Chris Drake - Google
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Herding Cats: How to Verify Timing Exceptions in Configurable IP
Author(s): Scott Evans - Sonics, Inc., Russell Roan - Synopsys
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| WC-03 ICV In-Design Methodology |
Reducing TAT and Achieving Timing Compatibility by New Metal Fill Flow Using In-Design ICV
Author(s): K.K. Lin, Jungsu An, Jinsuk Kim, Nandyala Ravi, Shinmo Kang, Jaehong Park - Samsung
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| WC-04 Memory BIST Embedded Test, Repair & Diagnostics and Hierarchical Test Solution |
Automated Memory BIST Insertion and Validation for SSD Controller-Based SoC
Author(s): Padma Nagaraja, Vaibhavi Sabharanjak, Sumanth Shantaram, Dinesh Kumar Tadepalli - SanDisk; Khachatur Armenyan - Synopsys
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