SNUG Silicon Valley 2015 Proceedings

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Complete Proceedings


User Papers and Presentations
MA-02 Frontend Implementation
An Optimal Approach for Datapath Implementation and Verification Methodology
Author(s): VSRP Kumar, Poonam Rani - Imagination Technologies
PaperPresentation

Who Put Assertions In My RTL Code? And Why? How RTL Design Engineers Can Benefit from the Use of SystemVerilog Assertions (1st Place - Best Presentation)
Author(s): Stuart Sutherland - Sutherland HDL
PaperPresentationSession Recording

MA-03 Low Power Implementation
Power Intent (UPF) Based Synthesis Flow for Multimillion Gate Complex SoCs
Author(s): Salima Lakhani, Purnima Ramakrishnan, Debajani Majhi - Broadcom
PaperPresentation

UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design Using VCLP
Author(s): Debajani Majhi, Liu Shaotao - Broadcom
PaperPresentation

MA-07 Circuit Simulation
HSPICE MOSRA Aging Simulation Considering Self-Heating Effect (2nd Place - Best Paper, Technical Committee Award)
Author(s): Jae-Gyung Ahn, Nick Lo, Ping-Chin Yeh - Xilinx; Zhaoping Chen, Weidong Liu, Joddy Wang - Synopsys
PaperPresentationSession Recording

MA-11 IP Lunch and Learn
Energy Harvesting, Sensors, and SoCs for the IoT Era
Author(s):
TutorialSession Recording

MA-12 Implementation Lunch and Learn
IC Compiler II - Accelerating Products to Market with the Power of 10X
Author(s):
Session Recording

MB-02 Physical Implementation
A Hybrid IC Compiler II-Based Flow for Rapid Design Closure
Author(s):
PaperPresentation

The Rubber Jigsaw Puzzle - Floorplanning for Network-on-Chip
Author(s): Jonah Probell, Byungchul Hong, Brian Huang - Arteris
PaperPresentationSession Recording

MB-03 Implementation Flows - IP for Memristor Development and Wireless Sensor Node Minimum Energy Design
Microcontroller Hard IP for Memristor Development ICs in 30 Days
Author(s): Richard Auletta - Hewlett Packard
PaperPresentationSession Recording

Minimum Energy Design for Sub-threshold Wireless Sensor Nodes
Author(s): Seng Oon Toh, James Myers - ARM
PaperPresentation

MB-04 VCS Save/Restore and Microprocessor Emulation
Improving Verification Productivity of Embedded C Tests Using the VCS Save/Restore Feature
Author(s): Neel Sonara - Broadcom; Amir Nilipour, Ajay Thiriaveedhi - Synopsys
PaperPresentation

Validating VISC Microprocessor in Emulation
Author(s): Hrishikesh Sankpal, Jongwen Chiou, Igor Lesik, Pirzad Motafram - Soft Machines
PaperPresentation

MB-05 VCS Performance and Golden UPF
Challenges and Benefits of Deploying a Master UPF Flow
Author(s): Chetan Avlani, Anand Lakshmanan, Ling Zhang - Broadcom; Amir Nilipour, Krishna Theja Avvaru, Vishwajith Singh - Synopsys
PaperPresentation

VCS Optimization Techniques for Multi-Chip Simulations
Author(s): Debashis Biswas - Cisco Systems
PaperPresentation

MB-08 Prototyping
ATOM Mobile SoC Performance and Power Architecture Exploration
Author(s):
PaperPresentation

MB-10 Conexant ASIP Implementation and IP Prototyping Kits
Design of Application Specific Processor for Far-field Voice Processing
Author(s): Ragnar Jonsson, Vineet Ganju - Conexant Systems
PaperPresentation

MC-05 Multi-Processor HW/SW Debug and Reusable Testbenches
Compile-time Parameter Distribution for Highly Reusable Testbenches (2nd Place - Best Presentation)
Author(s): Mark Glasser, Aman Arora - NVIDIA
PaperPresentationSession Recording

Multi Processor SoC Debug with Synopsys Hardware Software Debug Tool (Technical Chair Special Recognition Award)
Author(s): A. Mark Jesensky, Andy Sha - Analog Devices
PaperPresentationSession Recording

MC-09 Static Timing Analysis Flow Topics
Minimum Set of PrimeTime Timing Signoff Corners
Author(s): Alexander Tetelbaum - Abelite Design Automation
PaperPresentation

Sign-off Based Leakage Power Recovery in PrimeTime
Author(s): Sudhir Chandel - Marvell; Ahmet Gokcek - Synopsys
PaperPresentation

TA-02 Physical Implementation
Area-centric Reference Implementation Flow for ARM Mali Cost-Efficient GPUs
Author(s): Pierre-Alexandre Bou-Ach - ARM
PaperPresentationSession Recording

CTS Challenges of Complex Clock Structure Design (3rd Place - Best Presentation)
Author(s): Musab Alomari - Marvell
PaperPresentationSession Recording

TA-08 Statistical Characterization and Library Qualification
Tightening Hold Margins Using Monte Carlo Simulation
Author(s): Felipe Frantz - Synopsys
PaperPresentationSession Recording

TB-02 Multi-bit Implementation and Formal Verification
Reducing Clock Dynamic Power Using Multi-bit Register in High Performance Designs Using DCG/ICC
Author(s): Venkat Ghanta, Kranti Rajoli, Jaga Shamugavadivelu, Venkataraman Srinivasagam - Cisco Systems
PaperPresentation

TB-03 Test
Achieving High Compression Ratios with Cell-Constrained Designs Using DFTMAX Ultra
Author(s): Kalyana Kantipudi - Altera; Anand Gangwar - Synopsys
PaperPresentationSession Recording

Compression Chain Diagnosis
Author(s): Saravanan Gajendran - Cisco Systems; Anand Gangwar - Synopsys
PaperPresentationSession Recording

Volume Physical Diagnostics for Faster Yield Ramp
Author(s): Ramesh Saidapet, Paul Micheletti, Martin Parley, Karthik Sundaramurthy - Qualcomm Technologies; Aaron Henderson - Synopsys
PaperPresentationSession Recording

TB-04 Assertion Optimization, Full-chip Simulation, and AMS Behavioral Modeling
A Method to Dynamically Disable/Enable SystemVerilog Assertions
Author(s): Thinh Ngo - Broadcom
PaperPresentation

Flow for Equivalence Checking and Accuracy of Real Number Based Analog Models
Author(s): Rinkesh Patel, Nagina Bhandary - Microsoft; Vijay Akkaraju - Synopsys
PaperPresentation

Full-Chip Simulations, Keys to Success (3rd Place - Best Paper, Technical Committee Award)
Author(s): Dan Steinberg - Google
PaperPresentation

TB-05 GPU Emulation, Constraint Debug and Analysis, and UVM
Enabling Greater Reliability, Scalability, and Flexibility of GPU Emulation with a Hybrid Virtual Machine Based Approach
Author(s): Alex Starr, Andrew Ross - AMD
PaperPresentation

RESSL UVM Sequences to the Mat
Author(s): Jeff McNeal, Bryan Morris - Verilab
PaperPresentation

Using Verdi to Understand Constraint Gotchas, Debug Solver Failures, and Optimize Your Constraints (1st Place - Best Paper, Technical Committee Award)
Author(s): Rahul Chauhan - Broadcom; Jason Chen, Amir Nilipour - Synopsys
PaperPresentation

TB-08 Memory and POCV Aware Macro Sign-off and Characterization
SRAM Analysis and Characterization Using NanoTime for Memories
Author(s): Robert Murray - NVIDIA; Felipe R. Schneider - Synopsys
PaperPresentationSession Recording

WA-05 UVM
Navigating Your Way Toward UVM Version 1.2 - What's New About UVM v1.2
Author(s): David C. Black, Eileen R. Hickey - Doulos America
PaperPresentationSession Recording

UVM Message Display Commands Capabilities, Proper Usage and Guidelines
Author(s): Clifford E. Cummings - Sunburst Design
Presentation

WB-02 Custom Implementation
How to Make the Most Out of Your oaScripts by Using oaxPop Example
Author(s): Kevin Nesmith, Susan Carver - Silicon Integration Initiative; Christian Delbaere - Synopsys
PaperPresentation

Publication Only
Publish Only
EDA Flow for Differential Logic DPA Resistant Design
Author(s): Jimit Gadhia, Varun Nehru - Semi-Conductor Laboratory
Paper

Timing Exceptions Validation and Identification
Author(s): Rajkumar Agrawal, Manu Nagarajappa - Avago Technologies
Paper

Tutorials
MA-01 ICC II Technology
IC Compiler II Technology Tutorial
Author(s): Wei-Chun Chou - Synopsys
Tutorial

MA-04 Verification Direction
Synopsys Verification Direction
Author(s): Shantanu Ganguly - Synopsys

MA-07 Circuit Simulation
Technology Inflection Points - Planar to FinFET to Nanowire
Author(s): Victor Moroz - Synopsys
TutorialVideo

MA-08 Prototyping
Tales of Rapid Prototyping Heroes - Finding Multi-FPGA Partition Solutions Fast
Author(s): Ajay Jagtiani - Synopsys
TutorialVideo

MA-09 Signoff for Advanced Node SoCs
Large Scale Design STA - Hierarchical or Flat, Distributed or Single Machine: Which Way to Go for Timing Signoff?
Author(s): Robert Landy - Synopsys
Tutorial

What Every Designer Needs to Know About 16/14nm Library and STA Requirements
Author(s): Jennifer Pyon - Synopsys
Tutorial

MA-10 Optimizing DDR Memory Subsystems
Optimize DDR Memory Subsystems for Performance, Power, and Cost
Author(s): Asheesh Khare - Synopsys
Tutorial

MB-01 Frontend Implementation
Achieving Optimal Quality of Results Faster with Design Compiler
Author(s): Avinash Mane - Synopsys
Tutorial

MB-06 Software Testing with Coverity Part 1 of 2
Best Practices in Software Testing using Coverity Tools
Author(s): Yoel Gluck - Salesforce.com; Manish Gaur - VMWare; Andreas Kuehlmann -Synopsys
PresentationTutorialVideo

MB-07 Circuit Simulation
How the Custom Designer Simulation and Analysis Environment (SAE) Can Improve Your Circuit Simulation Productivity
Author(s): David Chou - Synopsys
TutorialVideo

MB-09 Signoff - POCV/LVF Variation Modeling
Latest Advancements for Handling Local Variation Effects in Timing Analysis
Author(s): Ayhan Mutlu, Duc Huynh - Synopsys
Tutorial

MB-10 Conexant ASIP Implementation and IP Prototyping Kits
Configure, Integrate, and Prototype IP in Minutes
Author(s): Hugo Neto - Synopsys

MC-02 Physical Implementation
Unlock IC Compiler II's "Power of 10X" Using Lynx Design System
Author(s): Devin Bright - Synopsys
TutorialVideo

MC-03 Test
SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System
Author(s): Gevorg Torjyan - Marvell; Yervant Zorian - Synopsys
TutorialVideo

MC-04 Verification Compiler Overview
Verification Compiler Overview
Author(s): Shekhar Mahatme, Shanmuga Sundaram - Synopsys
TutorialVideo

MC-06 Software Testing with Coverity Part 2 of 2
Best Practices in Software Testing using Coverity Tools - Continued
Author(s): Yoel Gluck - Salesforce.com; Andreas Kuehlmann - Synopsys

MC-07 Circuit Simulators Update
CustomSim Updates for Circuit Simulation
Author(s): Manju Paul Vattathara - Synopsys
TutorialVideo

Innovations in Fast and Accurate Transistor-level Simulation Using HSPICE, FineSim SPICE, and WaveView for Post Processing
Author(s): Khaled Nikro, Manu Velayudhan Pillai - Synopsys
TutorialVideo

MC-08 Prototyping
X-Ray Vision - High Visibility Multi-FPGA Debug for FPGA-Based Prototypes
Author(s): Peter Zhang - Synopsys
TutorialVideo

TA-03 Test
Meet Your Test Quality and Cost Goals on Schedule
Author(s): Adam Cron - Synopsys
Tutorial

TA-04 VC Apps Developer Forum
VC Apps Developer Forum - Enhancing Debug Productivity
Author(s): Albert Hsiung - MediaTek; Tom Anderson - Breker Systems; Yu-Chin Hsu, Rich Chang, Paul Huang - Synopsys
Tutorial

TA-05 ZeBu Tutorial
Leveraging ZeBu for Simulation Acceleration and Early SW Validation
Author(s): Prathamesh Joshi, Per Edstrom, Alex Wakefield - Synopsys
Tutorial

TA-06 Introduction to Software Quality and Security
Introduction to Software Quality and Security in the Emerging Internet of Things
Author(s): Andreas Kuehlmann - Synopsys
TutorialVideo

TA-07 Prototyping
Speed - Reveal Your Prototype's Performance Superpower - Synopsys HAPS High-Speed Time Domain Multiplexing (HSTDM)
Author(s): Naresh Maheshwari - Synopsys
TutorialVideo

TA-08 Statistical Characterization and Library Qualification
Standard Cell Qualification with SiliconSmart
Author(s): Antenor A. de Carvalho, Moninder Bansal - Synopsys
Tutorial

TA-10 Embedding Vision into SoCs
Embedding Vision into Your SoCs
Author(s): Pierre Paulin - Synopsys

TB-02 Multi-bit Implementation and Formal Verification
Formality and Formality Ultra Update
Author(s): Erin Hatch - Synopsys
TutorialVideo

Verilog-to-Verilog Equivalence Checking Using ESP-CV
Author(s): Dave Hedges - Synopsys
TutorialVideo

TB-06 FPGA Synthesis
ASIC to FPGA-based Prototype Conversion
Author(s): Ryan Racinez, Robert Perry - Synopsys
Tutorial

TB-07 Prototyping
Turning Your Power Spreadsheet into a Virtual Prototype for Energy-Aware Architecture Design
Author(s): Gururaj Rao - Synopsys
TutorialVideo

TB-08 Memory and POCV Aware Macro Sign-off and Characterization
Transistor Level Parametric On-Chip Variation (POCV) Setup and Analysis
Author(s): Norb Heindl, Chad Lawrence - Synopsys
TutorialVideo

TB-09 StarRC Advances in Performance and Process Technology - User Experiences
Fast ECO Extraction and Other Techniques for Optimizing Timing Closure TAT
Author(s): Amrita Sahoo - Synopsys
TutorialVideo

TB-10 SerDes PHY Selection and Interface IP Subsystems
Choosing the Right SerDes PHY IP to Differentiate Your SoC
Author(s): Rita Horner - Synopsys

Reduce the Effort and Cost of Integrating Interface IP Subsystems into SoCs
Author(s): Blessy Alexander - Synopsys

TC-03 Test Panel
Is It Possible to Lower Test Costs (Even More)?
Author(s): Leah Clark - Broadcom; Chris Coleman - Avago; Amitava Majumdar - Xilinx; Sohail Syed - Marvell; Rohit Kapur - Synopsys

TC-04 VC Formal and VC CDC
New Static Technologies - Clock Domain Crossing
Author(s): Namit Gupta - Synopsys
TutorialVideo

New Static Technologies - VC Formal Platform
Author(s): Anders Nordstrom - Synopsys
TutorialVideo

TC-05 Verdi Advanced Debug
Verdi Debug Platform (Planning, Coverage, HW/SW, AMS)
Author(s): Archie Feng, Betty Ching, Alex Wakefield - Synopsys
TutorialVideo

TC-07 Prototyping
Successful Complex GPU IP Implementation on Synopsys HAPS Platforms Using ProtoCompiler
Author(s): Andy Jolley - Synopsys
TutorialVideo

TC-09 Signoff Physical Verification
Current Density and Balanced Layout Checking Utilizing Programmable Extended ERC Checking with IC Validator
Author(s): Jeff Byrd - Synopsys
TutorialVideo

TC-10 IP for Energy-Efficient IoT Designs
IP That Will Drive Energy-Efficient IoT Designs
Author(s): Ron Lowman - Synopsys

WA-01 ICC II GUI
Getting Productive in the ICCII GUI
Author(s): Dan Guilin - Synopsys
TutorialVideo

WA-02 Custom Physical Implementation
Custom Design with FinFETs, Best Practices Designing Mixed-Signal IP
Author(s): Tom Quan - TSMC; Bob Lefferts - Synopsys
Tutorial

Handling Electromigration for Custom Design with FinFET Devices Using Custom Designer
Author(s): Denis Goinard - Synopsys
Tutorial

WA-03 Rail Implementation and Analysis
PrimeRail - Using Advanced Rail Analysis in the In-Design IC Compiler Implementation Flow
Author(s): Jack Ting - Synopsys
TutorialVideo

WA-04 VIP Test Suite
Utilizing VIP Test Suites
Author(s): Paul Graykowski - Synopsys
TutorialVideo

WA-06 FPGA Synthesis
Best Practices for Boosting Timing Performance Results in Your FPGA
Author(s): Paul Owens - Synopsys
TutorialVideo

WB-01 ICC Update
IC Compiler's Latest Release (2014.09) Delivers Significant Performance Power Area Improvements and Faster Closure on Emerging and Established Nodes
Author(s): Shoukyou Wang - Synopsys
TutorialVideo

WB-03 Test - Scan Diagnostics
Six Ways that Scan Diagnostics Drives Silicon Learning
Author(s): John Kim - Synopsys
TutorialVideo

WB-04 VCS 2014.12 Update
VCS-MX 2014.12 Update
Author(s): Rohit Narkar, Latha Venkatachari - Synopsys
TutorialVideo

WB-05 UVM-AMS
Verifying Mixed-Signal SoCs
Author(s): Kiran Maiya, Aravinda Ponduri - Synopsys
TutorialVideo

WB-06 FPGA Synthesis
How to Bring Up and Complete Your FPGA Design with Faster and Fewer Iterations
Author(s): Cheong Tse, Will Cummings - Synopsys
TutorialVideo

Panel Presentation
MC-01 FinFET Panel
Successfully Designing with FinFET
Author(s): Tom Arns - Altera; Mamta Bansal - Qualcomm; Kelvin Low - Samsung; Anwar Awad - Synopsys
Video

TC-01 ICC II R&D Panel
Enabling the Power of 10X on Advanced Designs Using IC Compiler II
Author(s): Dr. Michael Jackson, Dr. Neeraj Kaul, Dr. Pei-Hsin Ho, Dr. Aiqun Cao, Dr. Henry Sheng - Synopsys

Lunch and Learn Presentations
TA-11 Verification Lunch and Learn
Addressing SoC Complexity Across the Verification Continuum
Author(s):
Video

TA-12 Design Compiler Lunch and Learn
Accelerating Innovation with Design Compiler
Author(s):
Video

WB-08 - Lynx Lunch and Learn
Design Exploration to Accelerate PPA Closure of a Mobile Computing ARM Cortex-A53 Targeting Samsung Foundry 28LPP and 14LPP FinFET Technology with Lynx Design System
Author(s):

Combo
Designer Community Expo
Author(s):

User Presentation
MB-07 Circuit Simulation
Accelerating Analog IP Characterization & Verification by FlexIP Using Custom Design, HSPICE, and Custom WaveView
Author(s): Murilo Pilon Pessatti - Chipus
PresentationVideo

MB-08 Prototyping
Build and Integrate Your Own Custom IO Interfaces for Your HAPS-Based SOC Prototype
Author(s): Manohar Chandrasekhar - NVIDIA
Presentation

MB-09 Signoff - POCV/LVF Variation Modeling
Improving Design to Sign-off Correlation with Parametric On-chip Variation
Author(s):
Presentation

MC-10 Hardening GPUs with Memories and Libraries
Hardening Imagination's 16FF+ PowerVR Series7 GPU for Performance & Power with DesignWare HPC Design Kit
Author(s): John Herbert - Imagination Technologies

TA-01 In-Design Physical Implementation
Customer Experiences with IC Compiler In-Design for Metal Fill, Pattern Matching, and Automatic Double Patterning Fixing on Advanced Nodes
Author(s): Sameer Pujari - AMD; Peter Li - Huawei Technologies
PresentationVideo

TB-01 High-Performance Core Implementation
High-Performance, Energy Efficient Implementation of the ARM Cortex-A72 Processor Core in 16-nanometer FinFET Plus
Author(s): Haroon Gauhar - ARM; Joe Walston - Synopsys
PresentationVideo

Renesas Shares Highlights from Their Successful Implementation of an ARM Cortex-A57 MPCore Processor in 16-nm FinFET Plus Process Technology Using Synopsys Galaxy Design Platform
Author(s): Masakazu Nishibori - Renesas
PresentationVideo

TB-07 Prototyping
IP Power Modelling for Energy Aware Architecture Design
Author(s): Vita Vishnyakov - Microsoft; Alan Gibbons - Synopsys
PresentationVideo

TB-09 StarRC Advances in Performance and Process Technology - User Experiences
Achieving Highest Accuracy FinFET Extraction with StarRC "QuickCap Inside" Solution
Author(s): Tom Mahatdejkul - ARM
Presentation

Achieving Significant Productivity Improvement with StarRC Simultaneous Multi-Corner Solution - APM Experience
Author(s): Subbayyan Venkatesan - APM
Presentation

Fast, Accurate Extraction of High-Frequency Design using StarRC - AMD Update
Author(s): Khoa Nguyen, Jakrin Rojvongpaisal - AMD
Presentation

TC-02 Advanced Physical Implementation
Challenges and Solutions for 14nm Design Flows
Author(s): Tamer Ragheb – GLOBALFOUNDRIES; Jichun Zhou - Synopsys
PresentationVideo

WA-07 Optimizing Storage Infrastructure
Accelerating Library Characterization Through Infrastructure Optimization
Author(s): Bikash Roy Choudhury - NetApp; Ragini Suram - Synopsys
Presentation

An Apparatus for Quantifying and Replaying Consolidated EDA Workload
Author(s): Jignesh Bhadaliya - EMC
Presentation

WB-07 High-Performance Computing for Silicon Design
High-Performance Computing for Silicon Design
Author(s):
Presentation
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