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| Tutorials |
| MA-01 ICC II Technology |
IC Compiler II Technology Tutorial
Author(s): Wei-Chun Chou - Synopsys |
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| MA-04 Verification Direction |
Synopsys Verification Direction
Author(s): Shantanu Ganguly - Synopsys |
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| MA-07 Circuit Simulation |
Technology Inflection Points - Planar to FinFET to Nanowire
Author(s): Victor Moroz - Synopsys |
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| MA-08 Prototyping |
Tales of Rapid Prototyping Heroes - Finding Multi-FPGA Partition Solutions Fast
Author(s): Ajay Jagtiani - Synopsys |
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| MA-09 Signoff for Advanced Node SoCs |
Large Scale Design STA - Hierarchical or Flat, Distributed or Single Machine: Which Way to Go for Timing Signoff?
Author(s): Robert Landy - Synopsys |
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What Every Designer Needs to Know About 16/14nm Library and STA Requirements
Author(s): Jennifer Pyon - Synopsys |
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| MA-10 Optimizing DDR Memory Subsystems |
Optimize DDR Memory Subsystems for Performance, Power, and Cost
Author(s): Asheesh Khare - Synopsys |
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| MB-01 Frontend Implementation |
Achieving Optimal Quality of Results Faster with Design Compiler
Author(s): Avinash Mane - Synopsys |
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| MB-06 Software Testing with Coverity Part 1 of 2 |
Best Practices in Software Testing using Coverity Tools
Author(s): Yoel Gluck - Salesforce.com; Manish Gaur - VMWare; Andreas Kuehlmann -Synopsys |
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| MB-07 Circuit Simulation |
How the Custom Designer Simulation and Analysis Environment (SAE) Can Improve Your Circuit Simulation Productivity
Author(s): David Chou - Synopsys |
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| MB-09 Signoff - POCV/LVF Variation Modeling |
Latest Advancements for Handling Local Variation Effects in Timing Analysis
Author(s): Ayhan Mutlu, Duc Huynh - Synopsys |
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| MB-10 Conexant ASIP Implementation and IP Prototyping Kits |
Configure, Integrate, and Prototype IP in Minutes
Author(s): Hugo Neto - Synopsys |
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| MC-02 Physical Implementation |
Unlock IC Compiler II's "Power of 10X" Using Lynx Design System
Author(s): Devin Bright - Synopsys |
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| MC-03 Test |
SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System
Author(s): Gevorg Torjyan - Marvell; Yervant Zorian - Synopsys |
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| MC-04 Verification Compiler Overview |
Verification Compiler Overview
Author(s): Shekhar Mahatme, Shanmuga Sundaram - Synopsys |
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| MC-06 Software Testing with Coverity Part 2 of 2 |
Best Practices in Software Testing using Coverity Tools - Continued
Author(s): Yoel Gluck - Salesforce.com; Andreas Kuehlmann - Synopsys |
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| MC-07 Circuit Simulators Update |
CustomSim Updates for Circuit Simulation
Author(s): Manju Paul Vattathara - Synopsys |
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Innovations in Fast and Accurate Transistor-level Simulation Using HSPICE, FineSim SPICE, and WaveView for Post Processing
Author(s): Khaled Nikro, Manu Velayudhan Pillai - Synopsys |
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| MC-08 Prototyping |
X-Ray Vision - High Visibility Multi-FPGA Debug for FPGA-Based Prototypes
Author(s): Peter Zhang - Synopsys |
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| TA-03 Test |
Meet Your Test Quality and Cost Goals on Schedule
Author(s): Adam Cron - Synopsys |
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| TA-04 VC Apps Developer Forum |
VC Apps Developer Forum - Enhancing Debug Productivity
Author(s): Albert Hsiung - MediaTek; Tom Anderson - Breker Systems; Yu-Chin Hsu, Rich Chang, Paul Huang - Synopsys |
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| TA-05 ZeBu Tutorial |
Leveraging ZeBu for Simulation Acceleration and Early SW Validation
Author(s): Prathamesh Joshi, Per Edstrom, Alex Wakefield - Synopsys |
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| TA-06 Introduction to Software Quality and Security |
Introduction to Software Quality and Security in the Emerging Internet of Things
Author(s): Andreas Kuehlmann - Synopsys |
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| TA-07 Prototyping |
Speed - Reveal Your Prototype's Performance Superpower - Synopsys HAPS High-Speed Time Domain Multiplexing (HSTDM)
Author(s): Naresh Maheshwari - Synopsys |
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| TA-08 Statistical Characterization and Library Qualification |
Standard Cell Qualification with SiliconSmart
Author(s): Antenor A. de Carvalho, Moninder Bansal - Synopsys |
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| TA-10 Embedding Vision into SoCs |
Embedding Vision into Your SoCs
Author(s): Pierre Paulin - Synopsys |
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| TB-02 Multi-bit Implementation and Formal Verification |
Formality and Formality Ultra Update
Author(s): Erin Hatch - Synopsys |
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Verilog-to-Verilog Equivalence Checking Using ESP-CV
Author(s): Dave Hedges - Synopsys |
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| TB-06 FPGA Synthesis |
ASIC to FPGA-based Prototype Conversion
Author(s): Ryan Racinez, Robert Perry - Synopsys |
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| TB-07 Prototyping |
Turning Your Power Spreadsheet into a Virtual Prototype for Energy-Aware Architecture Design
Author(s): Gururaj Rao - Synopsys |
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| TB-08 Memory and POCV Aware Macro Sign-off and Characterization |
Transistor Level Parametric On-Chip Variation (POCV) Setup and Analysis
Author(s): Norb Heindl, Chad Lawrence - Synopsys |
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| TB-09 StarRC Advances in Performance and Process Technology - User Experiences |
Fast ECO Extraction and Other Techniques for Optimizing Timing Closure TAT
Author(s): Amrita Sahoo - Synopsys |
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| TB-10 SerDes PHY Selection and Interface IP Subsystems |
Choosing the Right SerDes PHY IP to Differentiate Your SoC
Author(s): Rita Horner - Synopsys |
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Reduce the Effort and Cost of Integrating Interface IP Subsystems into SoCs
Author(s): Blessy Alexander - Synopsys |
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| TC-03 Test Panel |
Is It Possible to Lower Test Costs (Even More)?
Author(s): Leah Clark - Broadcom; Chris Coleman - Avago; Amitava Majumdar - Xilinx; Sohail Syed - Marvell; Rohit Kapur - Synopsys |
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| TC-04 VC Formal and VC CDC |
New Static Technologies - Clock Domain Crossing
Author(s): Namit Gupta - Synopsys |
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New Static Technologies - VC Formal Platform
Author(s): Anders Nordstrom - Synopsys |
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| TC-05 Verdi Advanced Debug |
Verdi Debug Platform (Planning, Coverage, HW/SW, AMS)
Author(s): Archie Feng, Betty Ching, Alex Wakefield - Synopsys |
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| TC-07 Prototyping |
Successful Complex GPU IP Implementation on Synopsys HAPS Platforms Using ProtoCompiler
Author(s): Andy Jolley - Synopsys |
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| TC-09 Signoff Physical Verification |
Current Density and Balanced Layout Checking Utilizing Programmable Extended ERC Checking with IC Validator
Author(s): Jeff Byrd - Synopsys |
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| TC-10 IP for Energy-Efficient IoT Designs |
IP That Will Drive Energy-Efficient IoT Designs
Author(s): Ron Lowman - Synopsys |
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| WA-01 ICC II GUI |
Getting Productive in the ICCII GUI
Author(s): Dan Guilin - Synopsys |
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| WA-02 Custom Physical Implementation |
Custom Design with FinFETs, Best Practices Designing Mixed-Signal IP
Author(s): Tom Quan - TSMC; Bob Lefferts - Synopsys |
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Handling Electromigration for Custom Design with FinFET Devices Using Custom Designer
Author(s): Denis Goinard - Synopsys |
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| WA-03 Rail Implementation and Analysis |
PrimeRail - Using Advanced Rail Analysis in the In-Design IC Compiler Implementation Flow
Author(s): Jack Ting - Synopsys |
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| WA-04 VIP Test Suite |
Utilizing VIP Test Suites
Author(s): Paul Graykowski - Synopsys |
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| WA-06 FPGA Synthesis |
Best Practices for Boosting Timing Performance Results in Your FPGA
Author(s): Paul Owens - Synopsys |
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| WB-01 ICC Update |
IC Compiler's Latest Release (2014.09) Delivers Significant Performance Power Area Improvements and Faster Closure on Emerging and Established Nodes
Author(s): Shoukyou Wang - Synopsys |
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| WB-03 Test - Scan Diagnostics |
Six Ways that Scan Diagnostics Drives Silicon Learning
Author(s): John Kim - Synopsys |
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| WB-04 VCS 2014.12 Update |
VCS-MX 2014.12 Update
Author(s): Rohit Narkar, Latha Venkatachari - Synopsys |
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| WB-05 UVM-AMS |
Verifying Mixed-Signal SoCs
Author(s): Kiran Maiya, Aravinda Ponduri - Synopsys |
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| WB-06 FPGA Synthesis |
How to Bring Up and Complete Your FPGA Design with Faster and Fewer Iterations
Author(s): Cheong Tse, Will Cummings - Synopsys |
