SNUG Silicon Valley 2018 Call for Papers

Call for Papers is Now Open.

If you have used Synopsys technology to overcome difficult design issues and to accelerate your innovation, the SNUG community wants to hear from you!

Share your experience using Synopsys tools and IP at the 2018 Synopsys Users Group (SNUG), Silicon Valley. SNUG brings together more than 2000 Synopsys users, technologists and industry experts for Silicon Valley’s largest technical conference devoted to the challenges of electronic design and verification.

As a published SNUG author, you will increase your visibility in the local design and worldwide Synopsys user communities. In addition to the professional recognition, you will be eligible for significant cash awards (please check your company’s gift acceptance policy).

The call for papers is open September 12 – October 27, 2017. The SNUG Technical Committee will review the submitted proposals and notify authors about program acceptance by November 9, 2017.

We have a preliminary list of topics to get you started, but don’t let that limit your ideas or innovation:

Automotive

  • Implementing safety critical designs for automotive applications
  • FMEA/FMEDA tables, what’s required for ISO26262
  • Fault Validation of safety critical circuits using Z01X
  • How to improve your Automotive design’s verification environment using Certitude
  • Designing ISO26262 required In-System Test using Synopsys tools
  • High reliability design techniques for automotive designs
  • Using LYNX for ISO26262 Documentation requirements

Analog Mixed Signal Simulation

  • Application of Monte Carlo analysis to improve AMS circuit robustness with HSPICE, FineSim or CustomSim
  • Application of parallel computing to improve throughput of FinFET post-layout simulation with FineSim or CustomSim
  • How to minimize design margin with accurate reliability analyses including heat-aware EM, IR and device aging with CustomSim, FineSim or HSPICE
  • Best practices in mixed-signal verification with advanced digital verification methodology with CustomSim and VCS
  • How to verify power and signal integrity for multi-gigabit circuits with HSPICE
  • Application of CustomSim Circuit Check to find electrical rule violations in circuits

Custom Implementation

  • Productivity gain from using Custom Compiler Template Assistants (Symbolic Editor)
  • Productivity gain from using Custom Compiler In-Design Assistants (DRD, EM/IR, RCx)
  • Productivity gain from using Custom Compiler’s Co-Design with IC Compiler II
  • Case study: migrating to Custom Compiler from previous custom design tool
  • Tips for using Custom Compiler and SAE (simulation Analysis Environment) simulation and analysis environment to achieve robust analog design

Design Turnaround Time and Performance Optimization

  • Optimal design flow for digital Implementation of advanced 7nm designs
  • Accelerating turnaround time for large designs with Design Compiler Graphical and IC Compiler II
  • How to achieve best Performance, Power and Area for ARM CPUs
  • Best practices to maximize GF14 FDSOI technology benefits
  • Digital implementation guidelines to maximize benefits of TSMC’s 12nm process
  • How to accelerate physical signoff using massive parallel processing

FPGA Synthesis

  • Functional Safety is needed everywhere
  • Implement and confirm Quality of Safety Mechanism
  • Synplify Zynq solution Vivado out-of-context flow
  • Addressing higher design complexity with shortest time to design closure
  • Optimizing performance and area with the best quality of results
  • Versatile IP handling with encryption
  • Fast in-system debug and bug resolution 

IP Integration into SoCs

  • Interface IP: USB, PCI Express, DDR, MIPI, etc.
  • Processors: embedded ARC processors, embedded vision processors
  • Security – hardware root of trust, cryptography IP
  • Foundation IP – logic libraries, memory compilers
  • Integration of IP for automotive SoC designs
  • Integration of IP into IoT SoC designs
  • Integration of IP on advanced FinFET designs

Low Power Design and Analysis

  • Optimization techniques for low-power IoT designs

Machine Learning

  • Achieving QoR closure faster with machine learning in the Synopsys design flow

Silicon Test and Yield Analysis

  • Success with early RTL analysis, physically-aware and area-saving DFT, higher defect detection, lower pattern count/test time, faster and volume diagnostics
  • Highlighted applications include automotive, mobile, and processors

SoC Verification

  • Best practices for comprehensively verifying a low power design
  • How to model and verify system performance on a SoC or subsystem
  • Best practices for estimating power
  • Comprehensive design verification using formal methods
  • Improving simulation throughput with fine-grained parallelism (FGP)
  • Optimizing power for architecture design
  • Best practices for verification coverage planning and closure
  • Best practices for implementing CDC/RDC sign-off
  • Improving productivity using advanced debug techniques (including AMS and HW/SW debug)
  • Combining various verification techniques for bug-hunting
  • Increase visibility in your multi-FPGA Prototype with Global State Visibility

Software Bring-up

  • Accelerating software bring-up with emulation and prototyping
  • Improving software-driven hardware verification with hybrid-emulation
  • Using FPGA-based prototyping to accelerate system validation of IP and SoCs
  • Accelerating software development with virtual prototyping
  • Optimizing SoC performance and power with software-driven analysis 

Timing Analysis and Sign-off

  • Using parallel processing to accelerate full chip timing analysis and signoff
  • Using physical-aware ECO capabilities to improve PPA and accelerate timing closure

Copyright Statement

Please carefully read the following notice before submitting your written materials to the SNUG program.

By submitting materials to the SNUG program, you and your employer are giving Synopsys the following rights: to reproduce, publish and distribute the submitted materials on the SNUG web site for access by Synopsys employees, contractors, and licensees.

It is your responsibility to confirm that your employer agrees to the use described above. You and your employer reserve the right to modify the submitted materials at any time. Synopsys shall reproduce any copyright or other legal notices that you include in your submitted materials. Synopsys will not use your submitted materials for product marketing purposes without first obtaining your express written consent.

If you have any questions about this copyright statement, please contact the SNUG team before submitting your proposal.

For the complete author submission timeline, please view the Author's Kit.

Have a question? Ask your SNUG Team

We look forward to hearing from you!

Your Innovation, Your Community