|
| Tutorials |
| A1 Verification Directions |
Best Practices for Boosting Verification Performance
Author(s): Rafi Cohen - Synopsys |
|
| A2 Prototyping Direction |
HAPS-80 and HAPS ProtoCompiler
Author(s): Yair Dahan - Synopsys |
|
Synopsys Prototyping Direction
Author(s): Andrew Dauman - Synopsys |
|
| A3 Static Checks and Synthesis |
Designer Tool Kit Overview
Author(s): Igal Zeevi - Synopsys |
|
| A4 Implementation with ICC & ICCII |
IC Compiler II Delivers 10-20% Better Performance Power Area (PPA) On Advanced Designs
Author(s): Leon Rabinovich - Synopsys |
|
| A5 Custom Compiler and Flows |
Custom Compiler Technology Walk-Through
Author(s): Uri Golan - Synopsys |
|
| A6 Automotive Overview |
Synopsys Automotive Solutions
Author(s): Jeff Hutton - Synopsys |
|
| A7 IP Technology |
Addressing PCI Express 4.0 Controller Design Challenges at 16GT/s
Author(s): Richard Solomon - Synopsys |
|
Designing 7-nm IP, Bring It On Moore!
Author(s): Navraj Nandra - Synopsys |
|
| B1 Verification Methodology |
Verdi - Key Techniques to Speed Up Debug
Author(s): Yoram Granit - Synopsys |
|
| B2 FPGA and Prototyping Design |
Accelerate Your FPGA Design Schedules with Synplify Premier
Author(s): Paul Owens - Synopsys |
|
| B3 Low Power & DFT |
Achieving High Test Quality with Synopsys Recommended ATPG Flow
Author(s): Evgneni Polyakov - Synopsys |
|
Power Analysis Tools and Flows
Author(s): Avi Levi - Synopsys |
|
| B4 ECO |
Formality Ultra
Author(s): Avi Braun - Synopsys |
|
PrimeTime ECO
Author(s): Moshe Ashkenazi - Synopsys |
|
| B5 Circuit Simulation & Environment |
Custom Compiler Simulation Analysis Environment Walk-Through
Author(s): Alon Sasson - Synopsys |
|
| B6 Design for Automotive |
Accelerating the Path to a Safe and Secure SoC
Author(s): Fergus Casey - Synopsys |
|
DesignWare® ARC EV Embedded Vision Processors
Author(s): Tom Michiels - Synopsys |
|
| B7 USB TypeC & PCIe 4.0 |
Performance-Efficient Implementation of Robust Header Compression (ROHC) Using an Application-Specific Processor
Author(s): Patrick Verbist - Synopsys |
|
Successful SoC Implementation of USB Type-C and DisplayPort Alternate Mode
Author(s): Mick Posner - Synopsys |
|
| C2 Early Power Analysis |
Applying UPF 3.0 for Early, System-Level Power Analysis of SoCs with Micron DDR Memories
Author(s): Ohad Amrami - Synopsys |
|
| C3 Static Check & Debugging |
SpyGlass CDC and RDC - Clock and Reset Domain Crossing Verification
Author(s): Omri Margalit - Synopsys |
|
| C5 Analog Mixed-Signal |
Circuit Simulators Update: HSPICE, FineSim SPICE, and Custom WaveView ADV for Signal Integrity, Analog Simulations, and Waveform Post-Processing
Author(s): Alon Sasson - Synopsys |
|
CustomSim Updates for Circuit Simulation
Author(s): David Shaya - Synopsys |
|
| C6 Design for Automotive |
Building Performance Into Next Generation Embedded Devices
Author(s): Noam Babayof - Synopsys |
|
Reach ASIL Targets for Automotive Designs with Ethernet QoS IP and Certitude
Author(s): John Swanson - Synopsys |
|
| C7 IoT Design |
IoT-Optimized IP: Balancing Processor Performance and Energy Consumption
Author(s): Fergus Casey - Synopsys |
