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SNUG Israel 2015 Proceedings

 2017 | 2016  |  2015  |  2014  |  2013  

Complete Proceedings

User Papers and Presentations
A3 - IC Compiler II
A Hybrid IC Compiler II Based Flow for Rapid Design Closure
Author(s):
Presentation
A5 - Analog Mixed-signal Verification
Mixed-signal Verification of 15Gbit SerDes Using VCS AMS
Author(s): Alex Burdo - Marvell
PaperPresentation
B1 - Emulation Experience
Combining Emulation and Virtual Prototyping - The Whole is Greater Than the Sum of Its Parts
Author(s):
PaperPresentation

Moving Non-deterministic Failures to a Cycle-accurate and Deterministic Debug Environment
Author(s):
Presentation
B2 - FPGA and Prototyping Design
FPGA Prototyping Methodology - SoC Implementation Flow
Author(s):
PaperPresentation

Large-scale IP Prototyping
Author(s):
PaperPresentation
C1 - Verification User Experience
Internal UVM Stimulus - Unit-level Testing in a Top-level Environment
Author(s): Elihai Maicas - Qualcomm
Presentation
C3 - Advanced Static Timing Analysis and Sign-Off
POCV Use for Better STA
Author(s): Lior Zuker - AMD
Presentation
C4 - Design User Experience
Advanced CTS Balancing for Top Level Timing Closure
Author(s): Yehuda Peled - EZChip; Dror Rishin, Eddie Reizin - Synopsys
PaperPresentation

Always On Islands in Power Down Regions
Author(s): Meital Hollander, Avi Zukerman, Gilad Konsker, Michael Shuster, Noga Dayag - CSR
PaperPresentation
Tutorials
A2 - Prototyping Directions and Experience
Busting the Myths of Prototyping, Today and a Look into the Imminent Future
Author(s): Mick Posner - Synopsys
Tutorial

Tales of Rapid Prototyping Heroes Finding Multi-FPGA Partition Solutions Fast
Author(s): Yair Dahan - Synopsys
Tutorial
A3 - IC Compiler II
IC Compiler II and the Power of 10X - Technology Tutorial
Author(s): Neeraj Kaul - Synopsys
A5 - Analog Mixed-signal Verification
Verifying Mixed-signal SoCs Harnessing the Power of AMS Testbench and VCS AMS
Author(s): Helene Thibieroz - Synopsys
Tutorial
A6 - IP Development
Embedding Vision into Your SoCs
Author(s): Yankin Tanurhan - Synopsys
Tutorial

SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System
Author(s): Yervant Zorian - Synopsys
Tutorial
A7 - Coverity
Introduction to Software Quality and Security in the Emerging Internet of Things
Author(s): Ian Ashworth - Synopsys
Tutorial
B1 - Emulation Experience
Unified Compile - A Synopsys Verification Continuum Front-end Engine
Author(s): Doron Meiraz - Synopsys
B2 - FPGA and Prototyping Design
FPGA Debug Solutions
Author(s): Arnold Sher, Omer Tal - Synopsys
Tutorial
B3 - Solutions for Complex Implementation Challenges
Achieve Higher Productivity and Superior QoR with the Latest Advancements in the Design Compiler Family
Author(s): Eyal Odiz, Gal Hason, Neeraj Kaul - Synopsys
Tutorial
B4 - From FinFET to Nanowires
Engineering 7nm and 5nm Transistors and Library Cells - From FinFETs to Nanowires
Author(s): Victor Moroz - Synopsys
Tutorial
B6 - ARC Processor Applications
IP that Will Drive Energy-efficient IoT Designs
Author(s): John Talbot - Synopsys
Tutorial
B7 - System-level Design
Practical Virtual Prototyping
Author(s): Eshel Haritan, Ohad Amrami - Synopsys
Tutorial Tutorial
C1 - Verification User Experience
Certitude Updates
Author(s): Shaul Tzededk - Synopsys
Tutorial

New Technologies to Improve Your Coverage-Driven Verification Flow
Author(s): Yaron Ilani - Synopsys
Tutorial
C2 - FPGA Design Best Practices
Best Practices for Boosting Timing Performance Results in Your FPGA
Author(s): Paul Owens - Synopsys
Tutorial
C3 - Advanced Static Timing Analysis and Sign-Off
Latest Advancements for Handling Local Variation Effects in Timing Analysis
Author(s): Uri Halperin - Synopsys
Tutorial
C4 - Design User Experience
The Power to Change - Improving Your Design with PTPX
Author(s): Matti Katz - Synopsys
Tutorial
C5 - Custom Design and Flows for Mixed Analog/Digital Chips
Custom Design with FinFETs, Best Practices Designing Mixed-signal IP Custom Designer
Author(s): Uri Golan - Synopsys
Tutorial

How the Custom Designer Simulation and Analysis Environment (SAE) Can Improve Your Circuit Simulation Productivity
Author(s): Alon Sasson - Synopsys
Tutorial
C6 - IP Kits and DDR
Configure, Integrate, and Prototype IP in Minutes
Author(s): Hugo Neto - Synopsys
Tutorial

Optimize DDR Memory Subsystems for Performance, Power, and Cost
Author(s): Michael Chen - Synopsys
Tutorial
C7 - ASIP & ARC HS
Adding C-programmability to Data Path Design
Author(s): Patrick Verbist - Synopsys
Tutorial

High-Performance Cores for Low Power Design
Author(s): John Talbot - Synopsys
Tutorial
Silicon Valley 2017 Keynote

Dr. Peter Stone on “Learning and Multiagent Reasoning for Autonomous Robots”

Contact the SNUG Operations team for proceedings prior to 2013

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