SNUG Israel 2015 Proceedings

A5 - Analog Mixed-signal Verification

Mixed-signal Verification of 15Gbit SerDes Using VCS AMS
Author(s): Alex Burdo - Marvell

B1 - Emulation Experience

Combining Emulation and Virtual Prototyping - The Whole is Greater Than the Sum of Its Parts
Author(s):

Moving Non-deterministic Failures to a Cycle-accurate and Deterministic Debug Environment
Author(s):

B2 - FPGA and Prototyping Design

FPGA Prototyping Methodology - SoC Implementation Flow
Author(s):

Large-scale IP Prototyping
Author(s):

C1 - Verification User Experience

Internal UVM Stimulus - Unit-level Testing in a Top-level Environment
Author(s): Elihai Maicas - Qualcomm

C3 - Advanced Static Timing Analysis and Sign-Off

POCV Use for Better STA
Author(s): Lior Zuker - AMD

C4 - Design User Experience

Advanced CTS Balancing for Top Level Timing Closure
Author(s): Yehuda Peled - EZChip; Dror Rishin, Eddie Reizin - Synopsys

Always On Islands in Power Down Regions
Author(s): Meital Hollander, Avi Zukerman, Gilad Konsker, Michael Shuster, Noga Dayag - CSR

Tutorials

A2 - Prototyping Directions and Experience

Busting the Myths of Prototyping, Today and a Look into the Imminent Future
Author(s): Mick Posner - Synopsys

Tales of Rapid Prototyping Heroes Finding Multi-FPGA Partition Solutions Fast
Author(s): Yair Dahan - Synopsys

A3 - IC Compiler II

IC Compiler II and the Power of 10X - Technology Tutorial
Author(s): Neeraj Kaul - Synopsys

A5 - Analog Mixed-signal Verification

Verifying Mixed-signal SoCs Harnessing the Power of AMS Testbench and VCS AMS
Author(s): Helene Thibieroz - Synopsys

A6 - IP Development

Embedding Vision into Your SoCs
Author(s): Yankin Tanurhan - Synopsys

SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System
Author(s): Yervant Zorian - Synopsys

A7 - Coverity

Introduction to Software Quality and Security in the Emerging Internet of Things
Author(s): Ian Ashworth - Synopsys

B1 - Emulation Experience

Unified Compile - A Synopsys Verification Continuum Front-end Engine
Author(s): Doron Meiraz - Synopsys

B2 - FPGA and Prototyping Design

FPGA Debug Solutions
Author(s): Arnold Sher, Omer Tal - Synopsys

B3 - Solutions for Complex Implementation Challenges

Achieve Higher Productivity and Superior QoR with the Latest Advancements in the Design Compiler Family
Author(s): Eyal Odiz, Gal Hason, Neeraj Kaul - Synopsys

B4 - From FinFET to Nanowires

Engineering 7nm and 5nm Transistors and Library Cells - From FinFETs to Nanowires
Author(s): Victor Moroz - Synopsys

B6 - ARC Processor Applications

IP that Will Drive Energy-efficient IoT Designs
Author(s): John Talbot - Synopsys

B7 - System-level Design

Practical Virtual Prototyping
Author(s): Eshel Haritan, Ohad Amrami - Synopsys

C1 - Verification User Experience

Certitude Updates
Author(s): Shaul Tzededk - Synopsys

New Technologies to Improve Your Coverage-Driven Verification Flow
Author(s): Yaron Ilani - Synopsys

C2 - FPGA Design Best Practices

Best Practices for Boosting Timing Performance Results in Your FPGA
Author(s): Paul Owens - Synopsys

C3 - Advanced Static Timing Analysis and Sign-Off

Latest Advancements for Handling Local Variation Effects in Timing Analysis
Author(s): Uri Halperin - Synopsys

C4 - Design User Experience

The Power to Change - Improving Your Design with PTPX
Author(s): Matti Katz - Synopsys

C5 - Custom Design and Flows for Mixed Analog/Digital Chips

Custom Design with FinFETs, Best Practices Designing Mixed-signal IP Custom Designer
Author(s): Uri Golan - Synopsys

How the Custom Designer Simulation and Analysis Environment (SAE) Can Improve Your Circuit Simulation Productivity
Author(s): Alon Sasson - Synopsys

C6 - IP Kits and DDR

Configure, Integrate, and Prototype IP in Minutes
Author(s): Hugo Neto - Synopsys

Optimize DDR Memory Subsystems for Performance, Power, and Cost
Author(s): Michael Chen - Synopsys

C7 - ASIP & ARC HS

Adding C-programmability to Data Path Design
Author(s): Patrick Verbist - Synopsys

High-Performance Cores for Low Power Design
Author(s): John Talbot - Synopsys