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SNUG Israel 2014 Proceedings

2017 | 2016 | 2015 | 2014

Complete Proceedings

Speeches
Synopsys Keynote: Addressing Today’s Design Complexity Challenges Through Innovation and Collaboration
Industry Keynote: Growing and Addressing New Technology Directions
Author(s): Eyal Odiz, Vice President of Engineering, Synopsys, Inc. , Shai Cohen, Chief Operating Officer and Co-founder, Mellanox Technologies
User Papers and Presentations
B3 - Advanced Front–End Design and Updates
Latch Base Design - Alive and Kicking (Technical Committee Award Honorable Mention)
Author(s):
PaperPresentation
B5 - Analog Mixed-Signal Design Experience and Updates
Comprehensive AMS Flow for Submicron SoC Design (1st Place - Best Paper, Technical Committee Award)
Author(s):
PaperPresentation

Memory Characterization Using SiliconSmart Build-In FineSim-Pro Fast-SpiceTechnology
Author(s): Avi Parvin - TowerJazz
PaperPresentation
C1 -Verification User Experience
Automate Connectivity Validation Using Verdi's Novas Programmable Interface (NPI) (2nd Place - Best Paper, Technical Committee Award)
Author(s):
PaperPresentation

Constraint Callbacks
Author(s): Nadav Yutal - Qualcomm
PaperPresentation

Effective Flow for Advanced VLSI Process, False-Fails Protected, GL Timing Simulation Flow
Author(s): Rony Levin, Ilan Strulovici - Broadcom
PaperPresentation
C4 - Signoff and ECOs
Power Dedicated Area Optimization
Author(s):
PaperPresentation
C5 - Custom Design and Flows for Mixed Analog/Digital Chips
Full Custom Analog IC Design Flow Using Synopsys Tools
Author(s): Moshe Brauner - Inomize
PaperPresentation

Methodologies for Design of Digital Front End in Mixed Signal IC
Author(s): Shmulik Ajubel, Udi Nir - Toga Networks
PaperPresentation
Tutorials
A1 - Functional Verification & Prototyping
Verify! Prototype! Go! A Comprehensive Solution to SoC Verification and Prototyping Challenges
Author(s): Ken Nelsen- Synopsys
A3 - IC Compiler II
IC Compiler II and the Power of 10x: A Product Walk-Through
Author(s): JC Lin, Mark Richards - Synopsys
A5 - Analog and IP Development on FinFET
Physical IP Development on FinFET - There's Nothing Planar About It!
Author(s): Jamil Kawa - Synopsys
B1 - Emulation and Advanced Verdi Debugging
Going Beyond the Waveform: Advanced Debug Techniques in Verdi
Author(s): Arnold Sher - Synopsys
Tutorial

Protocol Analyzer
Author(s): Shlomi Levy, Synopsys
Tutorial

Verification of SoC Designs with ZeBu HW Emulator
Author(s): Ory Shelef - Synopsys
Tutorial
B2 - Hybrid Prototyping
Practical Virtual Prototyping - Architecture and Software Development
Author(s): Ohad Amrami - Synopsys
Tutorial
B3 - Advanced Front–End Design and Updates
Design Compiler 2013.12 Release Highlights
Author(s): Gal Hason - Synopsys
Tutorial
B4 - Low Power Design
Hierarchical Flow With Block Abstraction and Power Domains
Author(s): Pavel Vilk - Avnet
PaperPresentation

Low Power Flow (UPF) Update
Author(s): Eyal Odiz - Synopsys
Tutorial

Verdi Signoff-LP: Next-Generation Low-Power Static Verification
Author(s): Ziv Leshem - Synopsys
Tutorial
B5 - Analog Mixed-Signal Design Experience and Updates
Low-Power and Simulation Performance in Mixed-Signal
Author(s): Dr. Isaac Zafrany -Synopsys
Tutorial
B6 - USB 3.1 and Multi-Protocol High Speed PHY Tutorials
Addressing the Challenges of Multi-Protocol High Speed SERDES PHY Design
Author(s): Robert Fulton - Synopsys

Integrating USB 3.1 in Your Next SoC Design
Author(s): Didier Leclercq - Synopsys
Tutorial
B7 - Application-Specific Processors and DSPs
Application-Specific Processors and DSPs Provide Options to Enhance SOC Designs Performance and Energy Characteristics.
Author(s): Werner Geurts - Synopsys
Tutorial
C2 - Fast Prototyping
Better, Faster, Sooner: Tips and Tricks to Efficiently Achieve Timing Performance Goal
Author(s): Yair Dahan - Synopsys
Tutorial

Putting IP and Subsystem Prototyping on the Fast Track
Author(s): Mick Posner - Synopsys
Tutorial
C3 - Solutions For Complex Implementation Challenges
Analyzing Clock Mesh Circuits Using Analog Simulator
Author(s): Moshe Ashkenazi, Alon Sasson - Synopsys
Tutorial

Emerging Nodes Design With IC Compiler
Author(s): Leon Rabinovich - Synopsys
Tutorial

Routing DDR PHY Matched Length Signals Using Galaxy Custom Router
Author(s): Maor Aharon - Synopsys
Tutorial
C4 - Signoff and ECOs
ECO Implementation Assistance and Advanced Debugging Using Formality Ultra
Author(s): Shaul Ben-Dor - Synopsys
Tutorial

PrimeTime ECO - Now Physically Aware
Author(s): Evgeni Liberman - Synopsys
Tutorial
C5 - Custom Design and Flows for Mixed Analog/Digital Chips
Circuit Simulator Release Update: The Solution for Tomorrow's Challenge
Author(s): Dr. Isaac Zafrany -Synopsys
Tutorial
C6 - DDR4 and MIPI Tutorials
Faster DRAM: What You Need to Know About LPDDR4-3200, DDR4-3200, and Next-Generation DRAM
Author(s): Marc Greenberg - Synopsys
Tutorial

MIPI In Mobile Applications: Reducing Power with M-PHY, M-PCIe and USB SSIC
Author(s): Michael Chen- Synopsys
Tutorial
C7 - IoT and ARC Processors
High Speed Processing on an Embedded Budget
Author(s): Michael Thompson - Synopsys
Tutorial

Ultra-Low Power Processors and Subsystems for IoT
Author(s): Michael Thompson, Shlomi Dan - Synopsys
Tutorial
Workshop
B8 - ICC-Galaxy Custom Router - Workshop and Prizes!
Hands-on ICC-Galaxy Custom Router Workshop and Prize Draw
Author(s): Uri Golan - Synopsys
User Presentation
B2 - Hybrid Prototyping
Balancing Power Performance and User Experience Using Virtual Prototyping
Author(s):
Presentation

Decreasing T2M by Enabling Early Software design; VDK and HAPS
Author(s): Uri Shkolnik - Zoro Solutions
Presentation
B3 - Advanced Front–End Design and Updates
Faster Design Turnaround Using DC-Explorer for RTL Exploration
Author(s): Hatem Yazbek - Broadcom
Presentation
B7 - Application-Specific Processors and DSPs
An ARC 770D Based C-Programmable 400Gbps NPU Architected for Layer 2-7 Processing
Author(s): Erez Shaizaf - EZChip
Presentation

February 19, 2019
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