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| User Papers and Presentations |
| TA1 - IC Implementation |
Enhancing PPAS on High-Performance GPU Core with Next Generation PNR Tool
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Holistic Approach from Place to Post Route Optimization Targeting High Performance Design Closure Using IC Compiler II in New SI Technologies
Author(s): Manish Gupta, Shanavaz Hassan Khan - Qualcomm; Srikanth Basavapatna - Synopsys
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| TA2 - IC Implementation |
A Comprehensive Strategy to Resolve Design & Methodology Issues in High Performance ASICs (Best Paper Award)
Author(s): Sridhar Gunnam, Himanshu Gupte, Krishna Kotha - Broadcom
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Experience of Delivering Improved PPA & Closure Time Using IC Compiler II in High Performance x86-Microprocessor Design
Author(s): Sabeesh Balagangadharan, Mangaiarkkarasi Kannappan, Phaneendra Chennupati - AMD
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| TA3 - IC Implementation |
Developing the Next Generation P&R Flow for Complex Networking Designs
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Strategies to Implement Clock Tree Synthesis for Multiple Power Domain Design
Author(s): Swaroop Kane, Bhushan Kapadnis - Seagate
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| TB1 - IC Verification |
System Firmware Validation (SFV) – A Certitude Approach
Author(s): Jatin Savani - Qualcomm
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Using Verdi HW SW Debug to Accelerate SW Development
Author(s): Anand Venkitasubramani - Analog Devices; Dipankar Sarma - Synopsys
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| TB2 - IC Verification |
Augmenting Test Logic Validation Using Static Connectivity Verification
Author(s): Anuj Kumar, Ajay Kumar Dimri, Ambrish Chandra Pal - STMicroelectronics; Sami Akhtar - Synopsys
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Robust RDC Verification & Architectural Solutions to Eliminate Metastability Issues
Author(s): Neha Agarwal, Arjun Chowdhury, Chandan Gupta, Ankush Sethi - NXP
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| TB3 - IC Verification |
An Efficient Hierarchical Abstract Flow Approach for SoC Netlist Design
Author(s): Kaustubh Joshi, Abhijeet Kumar, Sivakumar Pinjala - Broadcom
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| TC1 - AMS |
Challenges & Practical Lessons Learned from Mixed Signal Verification of Multi-Protocol Compliant DDR PHY in 14nm LPP Process Node
Author(s): Dinesh Kumar Malviya, Sanathkrishna Holla, Avinash Bharadwaj Narasimhaswamy - Rambus Chip Technologies; Praveen Singh - Synopsys
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Comprehensive IP Circuit Reliability Using CustomSim Monte-Carlo & MOSRA
Author(s): Atul Bhargava, Florian Cacho, Parul Gangwar, Radhika Gupta - STMicroelectronics
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| TC2 - AMS |
A Novel Approach to Reusable & Time Optimized Methodology for Analysing DDR3 & DDR4 SSO Measurement Using Custom WaveView ADV
Author(s): Amit Kumar, Abhishek Jain - Microsemi; Krishna Sai Polisetty - Synopsys
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Implementing a SiliconSmart Based Flow for Characterizing DDR PHY Blocks
Author(s): Arun David, Arul Diraviyam, Ananth Haliyur Gopalakrishna, Mayank Gupta - Qualcomm
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| TC3 - AMS |
Augmentation of Static & Dynamic Checks for Electrical Verification of Mixed Signal Circuits (Best Paper Award)
Author(s): Deepon Saha, Krishnan Sukumar, Denitza Tchoevska, Emil Yushvaev - AMD
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NanoTime for Multi-Cycle Multi-Throughput Large Memory with Complex Design Challenges
Author(s): Harsha Bharadhwaj - NVIDIA
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| TD1 - Systems & IP |
Migrating to Synopsys ARC EM Processor for Accelerating Automotive Safety Product Designs
Author(s): Sourajit Jash, Senthil Kumaran, Kamatchi Saravanan A - Analog Devices
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Transition to SystemC: Challenges and Benefits
Author(s): Hemant Nigam, Chen Qian, Praveen Wadikar, Ling Yang - NVIDIA
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Verification of Automotive Complex Generic Timer Module (GTM-IP) at Pre-Silicon Phase by Means of Co-Simulation (Best Paper Award)
Author(s): Mukunda Byre Gowda, Karthikeyan Ramachandran - Bosch Engineering and Business Solutions
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| WA1 - IC Verification |
Formal Datapath Verification Against SLM
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Validation of Dynamic Clock Gating Designs Using Hierarchical Sequential Equivalence Checking
Author(s): Deepak Jindal, Maruthi Srinivas Narasimhan, Manik Tyagi - Qualcomm; Mahesh Parmar - Synopsys
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| WA2 - IC Verification |
Automated Code Coverage Waiver File Generation – Speed Up Verification Signoff
Author(s): Tushar Kanti Biswas, Deepanjan Roy - NVIDIA; Sanjana Bhattacharya, Raja Mahadevan - Synopsys
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Reuse of SystemC Models in RTL Verification (Best Paper Award)
Author(s): Mark Glasser, Kartik Mankad, Srinivasa Vadali, Praveen Wadikar - NVIDIA
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System Level Coherency Verification for Configurable Coherent Interconnects
Author(s): Sheshadri Kalkunte, Prabhu Kumar Karri, Shrinivas Sureban - Broadcom; Satyapriya Acharya - Synopsys
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| WA3 - IC Verification |
ABV with Bugscope – Quicker, Easier, Worthwhile!
Author(s): Rejoyce Ponnattil Jacob, Jasmin Rahiman - NXP
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Improving SoC/IP Quality Through RTL Design Parameter Analysis & Verification
Author(s): Prokash Ghosh - NXP; Mayank Digvijay Bindal - Synopsys
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| WB1 - IC Implementation |
Leveraging Multi-Level Physical Hierarchy Feature of Next Generation Physical Design Tool for Expeditious and Optimal Pin Planning in Hierarchical Designs
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| WB2 - IC Implementation |
Evolved Supply Set UPF Based Methodology
Author(s): Aman Jain - Seagate; Prasan Shanbhag - Synopsys
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Low Power Implementation Challenges in a Highly-Power Critical SoC
Author(s): Sitharam Ayathu, Pranjal Tiwari - Broadcom; Gaurav Ganeriwal, Prasan Shanbhag - Synopsys
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| WB3 - IC Implementation |
A Comprehensive CTS & Physical Aware Multibit Register Synthesis Methodology
Author(s): Aloke Mukherjee, Ujwala Ramachandra, Aravind Ramanujam - Qualcomm
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| WC1 - IC Design: Signoff |
Evaluation of HyperScale & Physically Aware ECO Flows on Multi-Million Hierarchical Design
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SSD SoC – Low Power Multi-Voltage Timing Closure Challenges
Author(s): Sathyanarayanan Chidambaram, Peter Lindberg, Ganesh Selvaraj - Broadcom; Ramanuj Mishra - Synopsys
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| WC2 - IC Design: Signoff |
An Effective Debugging of Clocks Issues for Faster Design Closure
Author(s): Akhilesh C. Mishra, Pawan Sehgal, Aditi Sharma - STMicroelectronics
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PrimeTime Based Optimal Power Optimization Methodology for FinFET-Based Designs (Best Paper Award)
Author(s): Sabeesh Balagangadharan, Amartya Mazumdar - AMD
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| WC3 - IC Design: Signoff |
Automation in Timing Exception Generation & Validation
Author(s): Om Srinath Janapareddy, Rajnikanth Kotagudem, Satyanarayana Medarametla, Raghu Pattipati - AMD
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| WD3 - IC Design: Test |
A Case Study on Launch – Off Extra Shift Implementation on DFTMAX Ultra Base Design (Best Paper Award)
Author(s): Omar Sharif Cherukur, Shreyans Rungta - Broadcom
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DFT Implementation Techniques for Multi-Power Domain Designs
Author(s): Aniruddha Bhasale, Jay Shah - Seagate
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Early RTL Testability & ATPG Coverage Analysis Using SpyGlass: A Case Study
Author(s): Mudasir Kawoosa, Preethi Ashok Kumar, Rajesh Mittal - Texas Instruments
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