SNUG India 2016 Proceedings

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Complete Proceedings


User Papers and Presentations
TA1 - IC Implementation
Enhancing PPAS on High-Performance GPU Core with Next Generation PNR Tool
Author(s):
Paper Presentation

Holistic Approach from Place to Post Route Optimization Targeting High Performance Design Closure Using IC Compiler II in New SI Technologies
Author(s): Manish Gupta, Shanavaz Hassan Khan - Qualcomm; Srikanth Basavapatna - Synopsys
Paper Presentation

TA2 - IC Implementation
A Comprehensive Strategy to Resolve Design & Methodology Issues in High Performance ASICs (Best Paper Award)
Author(s): Sridhar Gunnam, Himanshu Gupte, Krishna Kotha - Broadcom
Paper Presentation

Experience of Delivering Improved PPA & Closure Time Using IC Compiler II in High Performance x86-Microprocessor Design
Author(s): Sabeesh Balagangadharan, Mangaiarkkarasi Kannappan, Phaneendra Chennupati - AMD
Paper Presentation

TA3 - IC Implementation
Developing the Next Generation P&R Flow for Complex Networking Designs
Author(s):
Paper Presentation

Strategies to Implement Clock Tree Synthesis for Multiple Power Domain Design
Author(s): Swaroop Kane, Bhushan Kapadnis - Seagate
Paper Presentation

TB1 - IC Verification
System Firmware Validation (SFV) – A Certitude Approach
Author(s): Jatin Savani - Qualcomm
Paper Presentation

Using Verdi HW SW Debug to Accelerate SW Development
Author(s): Anand Venkitasubramani - Analog Devices; Dipankar Sarma - Synopsys
Paper Presentation

TB2 - IC Verification
Augmenting Test Logic Validation Using Static Connectivity Verification
Author(s): Anuj Kumar, Ajay Kumar Dimri, Ambrish Chandra Pal - STMicroelectronics; Sami Akhtar - Synopsys
Paper Presentation

Robust RDC Verification & Architectural Solutions to Eliminate Metastability Issues
Author(s): Neha Agarwal, Arjun Chowdhury, Chandan Gupta, Ankush Sethi - NXP
Paper Presentation

TB3 - IC Verification
An Efficient Hierarchical Abstract Flow Approach for SoC Netlist Design
Author(s): Kaustubh Joshi, Abhijeet Kumar, Sivakumar Pinjala - Broadcom
Paper Presentation

TC1 - AMS
Challenges & Practical Lessons Learned from Mixed Signal Verification of Multi-Protocol Compliant DDR PHY in 14nm LPP Process Node
Author(s): Dinesh Kumar Malviya, Sanathkrishna Holla, Avinash Bharadwaj Narasimhaswamy - Rambus Chip Technologies; Praveen Singh - Synopsys
Paper Presentation

Comprehensive IP Circuit Reliability Using CustomSim Monte-Carlo & MOSRA
Author(s): Atul Bhargava, Florian Cacho, Parul Gangwar, Radhika Gupta - STMicroelectronics
Paper Presentation

TC2 - AMS
A Novel Approach to Reusable & Time Optimized Methodology for Analysing DDR3 & DDR4 SSO Measurement Using Custom WaveView ADV
Author(s): Amit Kumar, Abhishek Jain - Microsemi; Krishna Sai Polisetty - Synopsys
Paper Presentation

Implementing a SiliconSmart Based Flow for Characterizing DDR PHY Blocks
Author(s): Arun David, Arul Diraviyam, Ananth Haliyur Gopalakrishna, Mayank Gupta - Qualcomm
Paper Presentation

TC3 - AMS
Augmentation of Static & Dynamic Checks for Electrical Verification of Mixed Signal Circuits (Best Paper Award)
Author(s): Deepon Saha, Krishnan Sukumar, Denitza Tchoevska, Emil Yushvaev - AMD
Paper Presentation

NanoTime for Multi-Cycle Multi-Throughput Large Memory with Complex Design Challenges
Author(s): Harsha Bharadhwaj - NVIDIA
Paper Presentation

TD1 - Systems & IP
Migrating to Synopsys ARC EM Processor for Accelerating Automotive Safety Product Designs
Author(s): Sourajit Jash, Senthil Kumaran, Kamatchi Saravanan A - Analog Devices
Paper Presentation

Transition to SystemC: Challenges and Benefits
Author(s): Hemant Nigam, Chen Qian, Praveen Wadikar, Ling Yang - NVIDIA
Paper Presentation

Verification of Automotive Complex Generic Timer Module (GTM-IP) at Pre-Silicon Phase by Means of Co-Simulation (Best Paper Award)
Author(s): Mukunda Byre Gowda, Karthikeyan Ramachandran - Bosch Engineering and Business Solutions
Paper Presentation

WA1 - IC Verification
Formal Datapath Verification Against SLM
Author(s):
Paper Presentation

Validation of Dynamic Clock Gating Designs Using Hierarchical Sequential Equivalence Checking
Author(s): Deepak Jindal, Maruthi Srinivas Narasimhan, Manik Tyagi - Qualcomm; Mahesh Parmar - Synopsys
Paper Presentation

WA2 - IC Verification
Automated Code Coverage Waiver File Generation – Speed Up Verification Signoff
Author(s): Tushar Kanti Biswas, Deepanjan Roy - NVIDIA; Sanjana Bhattacharya, Raja Mahadevan - Synopsys
Paper Presentation

Reuse of SystemC Models in RTL Verification (Best Paper Award)
Author(s): Mark Glasser, Kartik Mankad, Srinivasa Vadali, Praveen Wadikar - NVIDIA
Paper Presentation

System Level Coherency Verification for Configurable Coherent Interconnects
Author(s): Sheshadri Kalkunte, Prabhu Kumar Karri, Shrinivas Sureban - Broadcom; Satyapriya Acharya - Synopsys
Paper Presentation

WA3 - IC Verification
ABV with Bugscope – Quicker, Easier, Worthwhile!
Author(s): Rejoyce Ponnattil Jacob, Jasmin Rahiman - NXP
Paper Presentation

Improving SoC/IP Quality Through RTL Design Parameter Analysis & Verification
Author(s): Prokash Ghosh - NXP; Mayank Digvijay Bindal - Synopsys
Paper Presentation

WB1 - IC Implementation
Leveraging Multi-Level Physical Hierarchy Feature of Next Generation Physical Design Tool for Expeditious and Optimal Pin Planning in Hierarchical Designs
Author(s):
Paper Presentation

WB2 - IC Implementation
Evolved Supply Set UPF Based Methodology
Author(s): Aman Jain - Seagate; Prasan Shanbhag - Synopsys
Paper Presentation

Low Power Implementation Challenges in a Highly-Power Critical SoC
Author(s): Sitharam Ayathu, Pranjal Tiwari - Broadcom; Gaurav Ganeriwal, Prasan Shanbhag - Synopsys
Paper Presentation

WB3 - IC Implementation
A Comprehensive CTS & Physical Aware Multibit Register Synthesis Methodology
Author(s): Aloke Mukherjee, Ujwala Ramachandra, Aravind Ramanujam - Qualcomm
Paper Presentation

WC1 - IC Design: Signoff
Evaluation of HyperScale & Physically Aware ECO Flows on Multi-Million Hierarchical Design
Author(s):
Paper Presentation

SSD SoC – Low Power Multi-Voltage Timing Closure Challenges
Author(s): Sathyanarayanan Chidambaram, Peter Lindberg, Ganesh Selvaraj - Broadcom; Ramanuj Mishra - Synopsys
Paper Presentation

WC2 - IC Design: Signoff
An Effective Debugging of Clocks Issues for Faster Design Closure
Author(s): Akhilesh C. Mishra, Pawan Sehgal, Aditi Sharma - STMicroelectronics
Paper Presentation

PrimeTime Based Optimal Power Optimization Methodology for FinFET-Based Designs (Best Paper Award)
Author(s): Sabeesh Balagangadharan, Amartya Mazumdar - AMD
Paper Presentation

WC3 - IC Design: Signoff
Automation in Timing Exception Generation & Validation
Author(s): Om Srinath Janapareddy, Rajnikanth Kotagudem, Satyanarayana Medarametla, Raghu Pattipati - AMD
Paper Presentation

WD3 - IC Design: Test
A Case Study on Launch – Off Extra Shift Implementation on DFTMAX Ultra Base Design (Best Paper Award)
Author(s): Omar Sharif Cherukur, Shreyans Rungta - Broadcom
Paper Presentation

DFT Implementation Techniques for Multi-Power Domain Designs
Author(s): Aniruddha Bhasale, Jay Shah - Seagate
Paper Presentation

Early RTL Testability & ATPG Coverage Analysis Using SpyGlass: A Case Study
Author(s): Mudasir Kawoosa, Preethi Ashok Kumar, Rajesh Mittal - Texas Instruments
Paper Presentation

Publication Only
A Case Study on Formal Verification for Quality Verification Closure and Faster Time to Market
Author(s): Madabhushi Bharadwaj - AMD
Publish Only

Achieving Predictable & Faster Timing Convergence in Sub-nanometer Design
Author(s):
Publish Only

Crosstalk Noise Analysis and Closure Through PrimeTime SI
Author(s): Milap Darji - Qualcomm
Publish Only

Divide Scan Switching — Rule Power
Author(s): Surbhi Bansal, Bharat Londhe, Avinash Mendhalkar, Jay Shah - Seagate
Publish Only

Effective Approach for Differential Cell Timing Closure on SOC
Author(s): Prateek Jain, Natish Singla, Saurabh Srivastava - STMicroelectronics
Publish Only

Efficient ECO Implementation in Post Metal-Fill Layouts
Author(s):
Publish Only

Evolution of Power Aware Verification: What’s Next? Are We Done Yet?
Author(s):
Publish Only

Gate Oxide and Interlayer Dielectric Breakdown Verification, Developed on ERC Platform
Author(s):
Publish Only

Method & System to do Bitmap Verification for Memories
Author(s): Shreekanth Sampigethaya, Naveen Srivastava - AMD
Publish Only

Mitigating Congestion in Designs with High Net Density in 10nm Sub Micron Technology
Author(s): Sudhakar Alur, Avisekh Kumar, Prateek Omer, Ramanaryan Thukkaram - Qualcomm
Publish Only

Multi-Bit Register Banking: Features, Challenges Across Front End Flow and its Effect on Power Savings
Author(s): Robert Rouleau, Sampath Kumar Sambu, Girish T P, Shivaramakrishna Uddanti - AMD
Publish Only

Pipeline Based MBIST Area Overhead Optimization Using Star Memory System 4.X
Author(s): Prasad Prabhu, Nachiket Soman - Open-Silicon
Publish Only

PRODUCTIVITY APPS: Smart Techniques For SoC Verification and Faster TTM
Author(s): Arpit Gupta, Ishan Gupta, Anshul Jain, Abhijeet Khanna - Freescale
Publish Only

Smart TAT Reduction in DDR IO Characterization Using SiliconSmart & Hspice
Author(s): Shiv Mathur, Anand Sharma, Ramakrishnan Subramanian - SanDisk; Mohamed Filzer - Synopsys
Publish Only

Structural Clock Tree For High Performance Designs
Author(s): Bhupender Kumar, Thambi Prashank, Durga Sreepathy - Qualcomm
Publish Only

Too Many Macros, Too Easy to Deal
Author(s): Vijesj Devan, Lakshmi Chaya Kandula - Broadcom; Gaurav Ganeriwal, Sreedeep Sundaran - Synopsys
Publish Only

Tutorials
TA2 - IC Implementation
IC Compiler II 2016.03 Technologies to Meet Aggressive Performance, Power & Area Goals
Author(s): Pradeep Balasundaram - Synopsys
Tutorial

TB1 - IC Verification
Key Techniques to Speed Up Debug and Verification Closure – Recent Innovations in Verdi
Author(s): Tilak Chand Meka, Minu Thekekara - Synopsys
Tutorial

TB2 - IC Verification
Recent Advancements in SpyGlass CDC & RDC
Author(s): Paras Mal Jain - Synopsys
Tutorial

TC1 - AMS
Custom Compiler – Under the Hood R&D Walk-Through
Author(s): Graham Etchells, Narendra Shenoy - Synopsys
Tutorial

TC2 - AMS
Advanced Characterization Features in SiliconSmart
Author(s): Nanda Gopal - Synopsys
Tutorial

TD1 - Systems & IP
Optimizing User Software Using ARC Processor Extensions (APEX) in ARC EM Processors
Author(s): Abhishek Bit - Synopsys
Tutorial

WA1 - IC Verification
Essential Ingredients of Formal Based Verification Signoff
Author(s): Pratik Mahajan - Synopsys
Tutorial

WB1 - IC Implementation
Floorplanning Large Blocks Using IC Compiler II
Author(s): Vineet Kumar Kothari - Synopsys
Tutorial

WB2 - IC Implementation
Advanced Synopsys UPF-Based Flow to Perform Implementation & Verification
Author(s): Mahesh Narayan - Synopsys
Tutorial

WB3 - IC Implementation
Design Compiler Family 2016.03 Update & Best Practices for Faster Runtime on Large Designs
Author(s): Richa Soni - Synopsys
Tutorial

WC1 - IC Design: Signoff
PrimeTime ECO Tutorial
Author(s): Gauri Sankar Malla - Synopsys
Tutorial

WC2 - IC Design: Signoff
What’s New in StarRC: Advances for Improving Productivity and Efficiency
Author(s): Vikram Avaral - Synopsys
Tutorial

WC3 - IC Design: Signoff
Advanced Reporting with PrimeTime
Author(s): Ramakrishna R - Synopsys
Tutorial

WD1 - IC Design: FPGA
Accelerate Your Prototyping Productivity Leveraging HAPS with ProtoCompiler
Author(s): Ajay Jagtiani, Harish M K Gowda, William Luis - Synopsys
Tutorial

WD2 - IC Design: Test
Advancement in ATPG Technology & Case Studies
Author(s): Synopsys; Broadcom; SGS-TUV; STMicroelectronics; Toshiba
Tutorial

Vision Session
TA1 - IC Implementation
From Nanometers to Ångstroms, Physical Design in the Next Decade
Author(s): Marco Casale-Rossi - Synopsys
Vision

User Presentation
TC1 - AMS
Custom Compiler Adoption in STMicroelectronics for Design Development Efficiency
Author(s): Atul Bhargava - STMicroelectronics
Presentation

TD2 - Academia
Multi-Scale Modeling of Si1-xGex FinFETs: A Case Study of Material-to-Device Modeling
Author(s): Professor Swaroop Ganguly - IIT Bombay
Academia

SHAKTI - An India Microprocessor Initiative
Author(s): Professor V. Kamakoti- IIT Madras
Academia

TD3 - Academia
Formal Methods in EDA: Looking Beyond the Traditional Bastions
Author(s): Dr. Pallab Dasgupta - IIT Kharagpur
Academia

Ultra Dynamic Voltage Scalable Design of SRAMs
Author(s): Professor Bharadwaj Amrutur - IISc
Academia

WB1 - IC Implementation
Advanced Low Power, Multi-Million Design Planning Using IC Compiler II
Author(s): Varinder Kumar, Bhimender Saini - MediaTek; Suresh G, Gaurav Ganeriwal - Synopsys
Presentation

WB3 - IC Implementation
Addressing Design Challenges at Lower Nodes for Graphic Processor Unit Using DCG
Author(s): Amit Duggal - Qualcomm
Presentation

Design Compiler Version Qualification L-2016.03-SP1
Author(s): Sampath Kumar Sambu - AMD
Presentation

WD1 - IC Design: FPGA
A Novel Approach to Power Island Emulation in FPGA Platforms
Author(s):
Presentation

How ProtoCompiler Helps Us in Addressing Some of Our Prototyping Challenges
Author(s): Ramanan Sanjeevi Krishnan, Sivarama Prasad Valluri - NVIDIA
Presentation