| Speeches | | Keynote: | "Why Wait" - Harnessing Technology to Create a More Connected Society NOW
Author(s): Daaman Hejmadi, Vice President, Engineering - Qualcomm India Pvt. Ltd. |
| | User Papers and Presentations | | TA1 - IC Design - Implementation | Complex Power Grid Generation in Low Power Designs Using IC Compiler II
Author(s): Erhan Ergin, Divya Guruja - AMD |
| Quantum Improvement in Implementation Time of Large SoCs Using IC Compiler II
Author(s): Sitharam Ayathu, Alex Paul, Ravneet singh - Avago Technologies |
| | TA2 - IC Design - Implementation | High Performance Design Challenges on 16FF+ - Mitigations and Solutions (Best Paper Award)
Author(s): Himanshu Gupte, Priyank Laad, Akshay Pagariya, Piyush Sharma - Avago Technologies |
| Runtime and QoR - Best of Both Worlds with IC Compiler II
Author(s): Naveen Sharma - STMicroelectronics; Vineet Kumar Kothari - Synopsys |
| Tackling Advanced DRCs and DPT Violations Using In-Design Flow
Author(s): Keshava Murali - Qualcomm; Ananda Veerasangaiah - Synopsys |
| | TA3 - IC Design - Implementation | Graphics Floorplanning Using a Next-generation Design Planner
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| | TB1 - IC Verification | A Unique Methodology for Porting Non Synthesizable Behavioral SystemVerilog Checkers to Emulation
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| Making a Quality ZeBu Build for Enabling Software Bring Up
Author(s): Paresh Joshi - Freescale Semiconductors; Ashwani Sharma - Synopsys |
| | TB2 - IC Verification | UVM-based Verification Infrastructure for Multi-Channel Ethernet Design
Author(s): Anil Kumar A V, Sunita Jain, Mrinal Sarmah - Xilinx |
| | TC1 - AMS | Enhanced Verification of MIPI CSI2 Rx-PHY (DPHY) Using VCS-AMS Co-simulations
Author(s): Ratheesh Mekkadan - AMD |
| Equivalence Verification for Large and Complex Memory Structures
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| | TC2 - AMS | Conquering the Full Chip Electro Migration and IR Drop Analysis with Ramping Supply Using CustomSim-RA
Author(s): Bharat Bhushan, Atul Bhargava, Abhishek Jain - STMicroelectronics; Mridul Sengupta - Synopsys |
| Constraints Based Layout Regeneration for Mixed Signal Designs in Advanced Process Nodes (Best Paper Award)
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| Driving Analog Stimuli from a UVM Test Bench
Author(s): Amlan Chakrabarti, Satvika Challa, Raju Govinda - AMD |
| | TC3 - AMS | Enhancements in Full-Custom Flow to Mitigate Post-layout Challenges in Advanced Technology Nodes
Author(s): Atul Bhargava, Radhika Gupta, Bhawana Jain, Francois Lemery - STMicroelectronics |
| | TD2 - Systems and IP | High Performance Multimedia Subsystem Design Using Custom ASIP, Universal Multifunction Accelerator (UMA), and ARC-EM6 Microcontroller (Best Paper Award)
Author(s): Venu Kandadai, Rajashekar Reddy Merugu, Akhil Mithra, Vijaya Bhaskar Vejandla - Manjeera digital systems Pvt. Ltd. |
| Open-Source IoT OS on Synopsys ARC EM
Author(s): Sachin Ghadi, Shishir Tiwari - Open-Silicon |
| | TD3 - Systems and IP | A Fault Injection Framework Using Virtual Prototyping for Embedded Software Verification
Author(s): Rohit Ramachandraiah, Prasanth Sasidharan - Infineon |
| Automation to Validate Component Models in Saber
Author(s): Hemalatha Mekala, Kalyani Lagidi, Abinesh Raja, Bala Vinay Kumar - Robert Bosch |
| | WA1 - IC Verification | Coherency Verification of Complex Multi-Processor SoCs with Reusable VIP
Author(s): Sarath Chandran, Devendra Mulakkayala, Ravikrishnan Sree - NVIDIA; Smit Vora - Synopsys |
| Is X-optimism Burning my Low Power Design? (Best Paper Award)
Author(s): Harsh Garg - Freescale Semiconductor; Mayank Bindal - Synopsys |
| | WA2 - IC Verification | Comprehensive Verification of Camera Sub System of a High-end Mobile Platform
Author(s): Karan Gupta, Paras Gupta, Rajdeep Mondal - NVIDIA; Suneetha Suryadevara - Synopsys |
| Ensuring Quality of Design and Verification Using Certitude
Author(s): Sachin Jain, Tejbal Prasad - Freescale Semiconductors; Vipul Kumar - Smartplay Technologies; Ankit Garg - Synopsys |
| Performance Simulating APP for Real Applications
Author(s): Haneesh Endluri, Rajender Kumar - Cerium Systems |
| | WB1 - IC Design - Signoff | Reducing Number of Timing Analysis Corners Based On Statistical Analysis of Timing Violations (Best Paper Award)
Author(s): Gurkirat Singh - NVIDIA |
| Reducing TAT for Chip Tapeout Using HyperScale and Physical-aware ECO flow
Author(s): Dipesh Bajaj - ARM Embedded Technologies |
| | WB2 - IC Design - Signoff | An Effective Timing Constraint Methodology for Faster Design Closure
Author(s): ShivaRamakrishna Uddanti, Sravan ChaitanyaKota, Raghu Pattipati - AMD |
| | WB3 - IC Design - Signoff | Achieving Predictable QoR and Faster Signoff with Advanced Primetime ECO Features
Author(s): Tushar Tyagi, Sunil G D, Pradeep VS - Avago Technologies; Ramanuj Mishra - Synopsys |
| Faster Timing Convergence with Hyperscale Technology
Author(s): Mayank Dhananiwala, Naishad Parikh, Sandeep Parswanath, Prashank Thambi - Qualcomm |
| | WC1 - IC Design - Test | Advanced Scan Architecture for Next Generation Smartphone SoCs to Achieve Maximum Shift Power Reduction with Optimal Test Application Time (Best Paper Award)
Author(s): Mohanasundaram Selvam, Joju Joseph Zajo - MediaTek |
| Deploying DFTMAX Ultra on a Multi-Million Flop Hierarchical Design
Author(s): Suresh Kumar, Daryl Pereira, Sanjay Shinde, Aanand Venkatachalam - Avago Technologies |
| Modified SHS Methodology for Multi IEEE1500 Interface AMS IP
Author(s): Venkata Srinivas Kancharla, Umesh Parasar, Nitin Sharma, Mudit Srivastava - STMicroelectronics |
| | WC2 - IC Design - FPGA | Enabling Powergate Flows in FPGA Prototyping
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| | WC3 - IC Design - FPGA | Mitigating FPGA Prototyping Efforts For Large SoC Designs
Author(s): Vishwanath Linga, Rajeev Babu Morampudi - Moschip Semiconductor |
| Techniques Used to Partition a Complex-SoC into Multi- HAPS-70 System Using Certify (Best Paper Award)
Author(s): Ramanan Sanjeevi Krishnan, Sivarama Prasad Valluri - NVIDIA |
| | WD1 - Implementation - Front End and Low Power | A Novel Approach to Avoid Block Resynthesis for Big Functional/Backend ECOs (Best Paper Award)
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| EDA Flow for Differential Logic DPA Resistant Design
Author(s): Jimit Gadhia - SAC; Varun Nehru - SCL |
| Handling MUX Intense Data Path Designs
Author(s): Harshil Shah, Bhavin Bakhada, Kranthi Rajoli, Gourav Singhal - Cisco |
| Static Low Power Signoff on Multimillion Gate Design Using VC-LP
Author(s): Sayandeep Nag, Bhawna Pancholi, Ravindranatha SG - Qualcomm |
| | WD2 - Implementation - Front End and Low Power | Predict and Resolve the Effects of Full-Chip Design Planning on Block Synthesis for Hierarchical Implementation Flow
Author(s): Michael Barnes, Rajit Seahra, Girish TP, Sampath Kumar, Sambu ShivaRamakrishna Uddanti - AMD |
| | WD3 - Implementation - Front End and Low Power | Sequential Vectoring - Challenges in RLS Designs
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| | Publication Only | | Publish Only | A Novel MBIST Architecture and Implementation for Complex SoC
Author(s): Jaykumar Shah, Shyam Sundar - Analog Devices |
| Accurate Analysis of Latent Static Power in Custom CMOS Designs
Author(s): Deepon Saha, Animesh Sharma, Hariprasad TT - AMD; Vivek Sharma - Synopsys |
| Address ATPG Challenges on Design with Large Number of Asynchronous Clock Domains
Author(s): Misbahuddin Khaja, Fang Liu, Ming Liu - Mosys India |
| AMS Verification of High Speed Interfaces
Author(s): Gautham S Harinarayan, Garima Jain, Nitin Pant, Manmohan Rana - Freescale Semiconductors |
| An Effective Hybrid Strategy to Prototype USB3.0 IP on HAPS
Author(s): Abhijeet Dey - NVIDIA |
| Effective Constraint Management with PrimeTime GCA
Author(s): Sunil G D, Tushar Tyagi, Pradeep VS - Avago Technologies; Ramanuj Mishra - Synopsys |
| Gears & Knobs for Lower Area, Faster Performance, and Improved Runtimes
Author(s): Amitabh Goyal, Alaguraja Gopalakrishnan - Qualcomm; Deepti Pookat, Tapas Mandal - Synopsys |
| Moving Towards Implementing Very High Compression in Industrial SoC and Achieving It
Author(s): Swapnil Bahl, Shreyans Rungta - STMicroelectronics; Rahul Anand - Synopsys |
| Multi-bit Flip-flop Design Implementation Technique for Power Reduction in Sub-nanometer Designs
Author(s): |
| Parametric OCV (POCV) - Reducing Gap Between STA and SSTA
Author(s): Ankit Gupta, Naishad Parikh, Mayank Dhananiwala - Qualcomm |
| Predictability, Convergent and Consistent Flow Across DC-SPG, ICC, and PT for High Speed A9
Author(s): Nitin Kaushik, Deepika Madaan - STMicroeletronics; Vikas Garg - Synopsys |
| System-level Signal and Power Integrity Co-simulation of DDR4 Based on Power Aware IBISv5.0 Models
Author(s): Akhilesh Chandra Mishra, Yagya Dutt Mishra - STMicroelectronics; M.S. Hashmi - IIIT Delhi |
| To Gate or Not to Gate - Clock Gating Efficiency Methodology
Author(s): Sachin Scaria - Wipro Technologies; Srinivasa R STG - IBM |
| Turn-around Time Matters
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| UPF Support for Complex ARM Ios
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| | Tutorials | | TA1 - IC Design - Implementation | IC Compiler II - Accelerating Products to Market with the Power of 10X
Author(s): Neeraj Kaul, Sanjay Bali - Synopsys |
| | TA3 - IC Design - Implementation | High-Performance, Energy Efficient Implementation of the ARM Cortex-A72 Processor Core in 16-nanometer FinFET Plus (16FF+) Process Technology Using Synopsys Galaxy Design Platform
Author(s): Vidit Babbar - ARM; Gaurav Ganeriwal - Synopsys |
| | TB1 - IC Verification | Leveraging ZeBu for Simulation Acceleration and Early SW Validation
Author(s): Amit Sharma - Synopsys |
| | TB2 - IC Verification | Memory VIP Tutorial
Author(s): Gaurav Chugh - Synopsys |
| | TC1 - AMS | Custom Design at Advanced Nodes - Preserving Productivity for Process Privileges
Author(s): Narendra Shenoy - Synopsys |
| | TC3 - AMS | Innovations in Fast and Accurate Transistor-level SPICE Simulation Using HSPICE, FineSim SPICE, and WaveView for Post Processing
Author(s): Raj Sundararaman, Manju Vadilliarat - Synopsys |
| | TD1 - Coverity Platform | Secrets for Delivering Software - Faster and Cheaper
Author(s): Dhaval Shah - Synopsys |
| | TD2 - Systems and IP | Configure, Integrate, & Prototype IP in Minutes
Author(s): Sunil Raidurgam - Synopsys |
| | TD3 - Systems and IP | Optimize DDR Memory Subsystems for Performance, Power, and Cost
Author(s): Aravind Mothi - Synopsys |
| | WA1 - IC Verification | Verification Direction
Author(s): Vikas Gautam - Synopsys |
| | WA3 - IC Verification | Advanced Verdi Debug - Verdi Debug Platform (Planning, Coverage, HW/SW, AMS)
Author(s): Paul Huang - Synopsys |
| | WB1 - IC Design - Signoff | Latest Advancements for Handling Local Variation Effects in Timing Analysis
Author(s): Alireza Kasnavi - Synopsys |
| | WB2 - IC Design - Signoff | Library and STA Requirements for Improved STA Accuracy at Advanced Technology Nodes
Author(s): Sharath Narayana - Synopsys |
| | WB3 - IC Design - Signoff | StarRC Advances in Performance and Process Technology
Author(s): Ananda Veerasangaiah - Synopsys |
| | WC1 - IC Design - Test | Meet Your Test Quality and Cost Goals on Schedule
Author(s): Pramod Notiyath - Synopsys |
| | WC2 - IC Design - FPGA | X-Ray Vision - High Visibility Multi-FPGA Debug for FPGA-based Prototypes
Author(s): Peter Zhang - Synopsys |
| | WC3 - IC Design - FPGA | ASIC to FPGA-based Prototype Conversion
Author(s): Madhav Chikodikar - Synopsys |
| | WD2 - Implementation - Front End and Low Power | Achieving Optimal Quality of Results faster with Design Compiler
Author(s): Richa Soni - Synopsys |
| | WD3 - Implementation - Front End and Low Power | Formality and Formality Ultra Update
Author(s): Vikas Garg - Synopsys |
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