Share your experience using Synopsys tools and IP at the 2018 Synopsys Users Group (SNUG) in India. SNUG brings together Synopsys users, technologists and industry experts for your local technical conference devoted to the challenges of electronic design and verification.
As a published SNUG author, you will increase your visibility in the local design and worldwide Synopsys User communities. In addition to the professional recognition, you will be eligible for significant cash awards (please check your company’s gift acceptance policy).
The call for papers is open January 23 – February 26, 2018. The SNUG Technical Committee will review the submitted proposals and notify authors about abstract acceptance by March 16, 2018.
We have a preliminary list of topics to get you started, but don't let that limit your ideas or innovation in your submission:
- Accelerating Functional ECOs
- Accelerating SoC Verification (Verification Planning & Coverage, Analog-Mixed Signal, Verification IP (VIP), UVM Verification)
- Advanced Application Methodologies (Arm, Graphics/GPUs, Processors)
- Advanced Design Methodologies (High Performance, Low Power, Area Optimization, Time to Market)
- Applying Advanced Technologies (7/10/14/16nm, 3DIC, FinFET)
- Characterization (Standard Cell, Memory, I/Os, Complex Cells)
- Design and Verification Debug (RTL/Gates, Testbench, UVM, Protocol, UPF, Hardware/Software)
- Design Closure and IC Signoff (RTL Synthesis & Equivalence Checking, Place & Route, DRC/LVS, STA, Extraction)
- FPGA Design and Verification
- Full Custom Design and AMS Simulation Methodologies
- Functional Safety Verification (Fault Modeling, Fault Simulation)
- IP Integration into SoCs (Interfaces, Processors, Security, Foundation IP, etc.)
- Low Power Design, Analysis and Power Reduction Methodologies and Techniques, Static and Dynamic Low Power Verification
- Maximizing Results with Established Technology Nodes
- Prototyping (Virtual Prototyping, Hybrid Prototyping)
- Static and Formal Verification (Advanced Linting, Clock and Reset Domain Verification, Timing Exception Verification, Formal Property Verification, Formal Apps)
- System Design and Validation
- Test Automation (Design-for-Test (DFT), Yield Analysis, ATPG, Diagnostics, Compression)
Please carefully read the following notice before submitting your written materials to the SNUG program.
By submitting materials to the SNUG program, you and your employer are giving Synopsys the following rights: to reproduce, publish and distribute the submitted materials on the SNUG web site for access by Synopsys employees, contractors, and licensees.
It is your responsibility to confirm that your employer agrees to the use described above. You and your employer reserve the right to modify the submitted materials at any time. Synopsys shall reproduce any copyright or other legal notices that you include in your submitted materials. Synopsys will not use your submitted materials for product marketing purposes without first obtaining your express written consent.
If you have any questions about this copyright statement, please contact the SNUG team before submitting your proposal.
For the complete author submission timeline, please view the Author's Kit.