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User Papers and Presentations |
A1 Digital - Design |
Entering FD-SOI Era - Ease of Design Combined with Tunable Performance/Power Optimization Using GLOBALFOUNDRIES 22FDx Technology Author(s): Stefan Block, Wolfgang Daub, Juergen Dirks, Farid Labib, Rainer Mann, Haritez Narisetty, Herbert Preuthen, Fulvio Pugliese, Tamer Ragheb, Richard Trihy - GLOBALFOUNDRIES |
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Gated Power Network Design and Implementation of High-End ARM® GPU Cores in Mission and Scan Modes Author(s): Evgeny Zenin, Dmitry Korolev - JSC Baikal Electronics; Dmitry Radchenko - Synopsys |
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Reduce Chip Area in a High Routing Congested ARM CortexM3 Design Author(s): Jens Mayer - Micronas New Technologies |
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A2 Digital - Test |
How Logic and Memory BIST Can Help to Address Some Functional Safety Requirements in Automotive ICs (Technical Committee Award) Author(s): Christophe Eychenne - Robert Bosch SAS |
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Increasing Test Coverage with Dedicated Scan Enable for ICG's Author(s): Carsten Wegener, Hans Martin von Staudt - Dialog Semiconductor; Frank Nolting - Synopsys GmbH |
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Optimisation of DFTMAX Ultra Scan Patterns (Technical Committee Award Honorable Mention) Author(s): Richard Illman - Dialog Semiconductor |
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A3 Digital - Verification I |
Enriching Your Simulation Work Flow with Behavioral SystemC Models Author(s): Thomas Leitner - DMCE GmbH & Co KG |
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One SoC, Two Verification Methods (Formal and Simulation), One Common Coverage Metric Author(s): Andreas Pachl, Stephanie Legeleux, Dirk Heisswolf - NXP Semiconductor |
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The S32V234 Vision Processor VDK: A Virtual Prototype for ADAS Applications Author(s): Manfred Thanner, Armin Strobl, Bogdan Chircu-Mare, Rosta Hulik, Tomas Babinec, Eric Simard, Ali Osman Ors, Stephan Herrmann - NXP Semiconductor; Aneesh Bhasin, Prakash Sahay, Gunnar Braun - Synopsys |
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A4 Analog - Infrastructure |
De-Mystifying TCL Custom Application Creation in Custom Compiler, with Automatic AMS IP Block Documentation as an Example Author(s): Vitalii Kudriavtcev - Elmos Semiconductor AG |
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Development and Verification of a Truly Interoperable PDK at ams Author(s): Bertram Winter - ams AG |
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Standardized PDK Setup in Design Projects Author(s): Gernot Koch - Micronas GmbH |
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A5 System - Prototyping |
Automated Integration of MathWorks® Simulink® Signal Flow Graph Models into Synopsys® Virtualizer™-based Virtual Prototypes (2nd Place - Best Paper) Author(s): Andreas Mauderer - Robert Bosch GmbH; Alexander Schreiber - The MathWorks GmbH; Jerome Chevalier - The MathWorks, Inc.; Jan-Hendrik Oetjens - Robert Bosch GmbH |
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Deploying the ProtoCompiler Tool for Targeting Complex FPGA-based Prototyping Platforms in a Highly Automated Approach Author(s): Igor Suetinov - JSC Baikal Electronics; Philipp Jacobsohn - Synopsys GmbH |
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FPGA Prototyping of a Complete System-on-Chip with the HAPS-DX7 (3rd Place - Best Paper) Author(s): Sandro-Diego Wölfle - Hyperstone GmbH |
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B1 Digital - Low Power |
Generating Accurate Gate Level Activity for Power Analysis, Prior to Back Annotated Timing Simulation (1st Place - Best Paper) Author(s): Carsten Rau - Infineon Technologies AG |
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Partial State Retention with Scan Chains Author(s): Hendrik Feldkaemper, Tin Lam, Axel Klein - Toshiba Electronics Europe GmbH |
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Quo Vadis Power? Early Power Assessment over Development Cycle Author(s): Carsten Rau - Infineon Technologies AG |
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B2 Digital - Signoff |
Bottom-up Reusable Timing Constraints Development and Validation Methodology in Case of Multiplexed External Interfaces Author(s): Samuel Intiso, Jonas Oxenholt, Jan Bengtsson - Axis Communications AB |
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B3 Digital - Verification II |
Mastering Reactive Slaves in UVM Author(s): Mark Litterick, Jeff Montesano - Verilab |
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Yet Another Memory Manager (YAMM) Author(s): Ionut Tolea, Andrei Vintila - AMIQ Consulting SRL |
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B4 Analog Verification I |
A SPICE based MOSFET Calculator Author(s): Erich Gottlieb - Micronas GmbH |
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SAE Based Top Level Verification of CMOS Analog Circuits Author(s): Adalbert Jordan - Micronas GmbH |
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B5 Analog - Verification II |
Innovative Propagation Methodology for Diodes and Clamps by Using TCL-CCK Advanced Capabilities in Synopsys Circuit Check Author(s): Mauro Fragnoli, Alessandro Valerio, Luca Togni, Salvatore Santapa’, Pierluigi Daglio, Paolo Ghigini - STMicroelectronics; Carlo Borromeo - Synopsys |
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System Level Verification with CustomSim PCM (Phase Change Memory) Built-in Cell Author(s): Chantal Auricchio, Alberto Balzarotti, Massimo Borghi, Alessandro Valerio - STMicroelectronics; Tien Pham, Claudio Rallo - Synopsys |
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C5 Electrical Rule Checking |
Extended ERC for Full Chip Verification to Avoid ESD and Design Related Pitfalls Author(s): Heiko Pera - ELMOS Semiconductor AG |