In-Design Metal Fill Insertion for Faster Timing Convergence
Author(s): Raphael Gras, Ahmed Oumina - STMicroelectronics; Emmanuel Pluchart - Synopsys

Paper

Presentation

Integrating Aging Aware Timing Analysis into PrimeTime
Author(s): Shushanik Karapetyan, Ulf Schlichtmann - Technische Universität München

Paper

Presentation

A2 - Implementation - Low Power & Test

Efficiently Reducing Dynamic Power Consumption of Power Management Integrated Circuits (PMICs)
Author(s): Esra Sahin - Dialog Semiconductor

Paper

Presentation

MTCMOS Based Low Power Implementation in GLOBALFOUNDRIES 28nm Process Using UPF2.0 - A Case Study (Technical Committee Award)

Author(s): Farid Labib - GLOBALFOUNDRIES; Ramin Navai - Synopsys

Paper

Presentation

Optimization of Power Consumption During Scan Testing - Power-Aware DFT
Author(s): Jean-Marie Martin - Nagravision SA

Paper

Presentation

A3 - Virtual Prototyping

Automated Generation of Synopsys Virtualizer Architectures Based on Hardware Descriptions in IP-XACT (1st Place - Best Paper)

Author(s): Venkateshwar Krishnamurthy, Andreas Mauderer, Jan-Hendrik Oetjens - Robert Bosch GmbH; Thomas Schumann - Hochschule Darmstadt

Paper

Presentation

IQ Over IP - How to Connect an LTE Radio Communication Tester to a Virtual Platform
Author(s): Peter Blöcher, Nicolai Heilemann - Ericsson Modems

Paper

Presentation

Parallel Simulation of a Virtual Platform for an Industrial Automation System - With MultiSim
Author(s): Kai Liu, Andreas von Schwerin - Siemens AG

Paper

Presentation

A4 - Analog Verification

A Reusable and Scalable Approach for Analog Focused Mixed-signal Verification (3rd Place - Best Paper)

Author(s): Roland Lengfeldner - Infineon Austria AG

Paper

Presentation

CCK - Using TCL API with Static Voltage Propagation for Detection of ESD and Stress Violations
Author(s): Catalin Tugui, Lior Dagan - Dialog Semiconductor

Paper

Presentation

Transistor Level Static Checks in an Automotive Design-Environment Using Synopsys CCK (Technical Committee Award Honorable Mention)

Author(s): Erich Gottlieb - Micronas GmbH

Paper

Presentation

A5 - Digital Verification - Assertions, Fault Injection, & Analog Modeling

Fault Analysis Best Practices with Certitude
Author(s): Luca Bizjak, Massimiliano Fieni, Meng Sun - Infineon Technologies Austria AG

Paper

Presentation

How to Use the New System Verilog Nettypes to Address the Analog SoC Integration Verification
Author(s): Joachim Geishauser, Thomas Theisen - Freescale Halbleiter Deutschland GmbH

Paper

Presentation

SystemVerilog Assertions Verification with SVAUnit
Author(s): Ionut Ciocirlan, Andra Radu - AMIQ Consulting

Paper

Presentation

A6 - Digital Verification - UVM

Stepwise Migration to UVM in the Course of One SoC Project
Author(s): Stephan Rüttiger, Michael Rohleder, Cristian Macario - Freescale

Paper

Presentation

Using Synopsys VCS to Connect a Company's SystemC Verification Methodology to Standard Concepts of UVM
Author(s): Frank Poppen - OFFIS Institute for Information Technology; Marco Trunzer, Jan-Hendrik Oetjens - Robert Bosch GmbH

Paper

Presentation

Versatile UVM Scoreboarding
Author(s): Jacob Sander Andersen, Peter Jensen, Kevin Steffensen - SyoSil Aps

Paper

Presentation

B3 - System Design and HW Prototyping

Design of an ISA-Extension for an Image Processing ASIP
Author(s): Jones Y. Mori, Frederik Kautz, Michael Hübner - Ruhr-University Bochum

Paper

Presentation

Multi-core SoC Mixed Mode Prototyping Using Synopsys HAPS-70 System
Author(s): Pavel Osipenko, Grigory Khrenov, Grigory Antyufeev, Ivan Averin, Andrey Didenko, Maxim Furseev, Constantine Gurin, Igor Suetinov - Baikal Electronics, Russia

Paper

Presentation

Virtual Development on Mixed Abstraction Levels - An Agricultural Vehicle Case Study
Author(s): Matthias Jung, Songlin Piao, Thiyagarajan Purusothaman, Xiao Pan, Christoph Grimm, Karsten Berns, Norbert Wehn - University of Kaiserslautern; Thomas Kuhn - Fraunhofer Institute IESE

Paper

Presentation

B4 - Analog Verification

Analog/Mixed-signal Data Management with Custom Designer and Cliosoft
Author(s): Thilo Schmidt - Elmos Semiconductor AG

Paper

Presentation

B6 - Digital Verification - AMS, UVM, & Debugging

Extending New Verification Techniques to Mixed-signal SoCs with VCS AMS
Author(s): Alessandro Valerio, Mauro Scandiuzzo, Pierluigi Daglio - STMicroelectronics; Helene Thibieroz, Massimo Prando, Carlo Borromeo - Synopsys

Paper

Presentation

Navigating Your Way Toward UVM Version 1.2
Author(s): John Aynsley, David C. Black, Eileen R. Hickey - Doulos

Paper

Presentation

Tutorials

B1 - Implementation - Synthesis

Achieving Optimal Quality of Results faster with Design Compiler
Author(s): Jean-Pierre Popieul - Synopsys

Tutorial

B4 - Analog Verification

How the Custom Designer Simulation and Analysis Environment (SAE) Can Improve Your Circuit Simulation Productivity
Author(s): Uwe Trautner - Synopsys

Tutorial