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| User Papers and Presentations |
| A1 - Implementation - Timing & STA |
Generating Scan Patterns for Scan Chains with Intermittent Timing Problems (2nd Place - Best Paper)
Author(s): Richard Illman - Dialog Semiconductor |
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In-Design Metal Fill Insertion for Faster Timing Convergence
Author(s): Raphael Gras, Ahmed Oumina - STMicroelectronics; Emmanuel Pluchart - Synopsys |
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Integrating Aging Aware Timing Analysis into PrimeTime
Author(s): Shushanik Karapetyan, Ulf Schlichtmann - Technische Universität München |
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| A2 - Implementation - Low Power & Test |
Efficiently Reducing Dynamic Power Consumption of Power Management Integrated Circuits (PMICs)
Author(s): Esra Sahin - Dialog Semiconductor |
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MTCMOS Based Low Power Implementation in GLOBALFOUNDRIES 28nm Process Using UPF2.0 - A Case Study (Technical Committee Award)
Author(s): Farid Labib - GLOBALFOUNDRIES; Ramin Navai - Synopsys |
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Optimization of Power Consumption During Scan Testing - Power-Aware DFT
Author(s): Jean-Marie Martin - Nagravision SA |
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| A3 - Virtual Prototyping |
Automated Generation of Synopsys Virtualizer Architectures Based on Hardware Descriptions in IP-XACT (1st Place - Best Paper)
Author(s): Venkateshwar Krishnamurthy, Andreas Mauderer, Jan-Hendrik Oetjens - Robert Bosch GmbH; Thomas Schumann - Hochschule Darmstadt |
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IQ Over IP - How to Connect an LTE Radio Communication Tester to a Virtual Platform
Author(s): Peter Blöcher, Nicolai Heilemann - Ericsson Modems |
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Parallel Simulation of a Virtual Platform for an Industrial Automation System - With MultiSim
Author(s): Kai Liu, Andreas von Schwerin - Siemens AG |
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| A4 - Analog Verification |
A Reusable and Scalable Approach for Analog Focused Mixed-signal Verification (3rd Place - Best Paper)
Author(s): Roland Lengfeldner - Infineon Austria AG |
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CCK - Using TCL API with Static Voltage Propagation for Detection of ESD and Stress Violations
Author(s): Catalin Tugui, Lior Dagan - Dialog Semiconductor |
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Transistor Level Static Checks in an Automotive Design-Environment Using Synopsys CCK (Technical Committee Award Honorable Mention)
Author(s): Erich Gottlieb - Micronas GmbH |
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| A5 - Digital Verification - Assertions, Fault Injection, & Analog Modeling |
Fault Analysis Best Practices with Certitude
Author(s): Luca Bizjak, Massimiliano Fieni, Meng Sun - Infineon Technologies Austria AG |
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How to Use the New System Verilog Nettypes to Address the Analog SoC Integration Verification
Author(s): Joachim Geishauser, Thomas Theisen - Freescale Halbleiter Deutschland GmbH |
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SystemVerilog Assertions Verification with SVAUnit
Author(s): Ionut Ciocirlan, Andra Radu - AMIQ Consulting |
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| A6 - Digital Verification - UVM |
Stepwise Migration to UVM in the Course of One SoC Project
Author(s): Stephan Rüttiger, Michael Rohleder, Cristian Macario - Freescale |
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Using Synopsys VCS to Connect a Company's SystemC Verification Methodology to Standard Concepts of UVM
Author(s): Frank Poppen - OFFIS Institute for Information Technology; Marco Trunzer, Jan-Hendrik Oetjens - Robert Bosch GmbH |
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Versatile UVM Scoreboarding
Author(s): Jacob Sander Andersen, Peter Jensen, Kevin Steffensen - SyoSil Aps |
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| B3 - System Design and HW Prototyping |
Design of an ISA-Extension for an Image Processing ASIP
Author(s): Jones Y. Mori, Frederik Kautz, Michael Hübner - Ruhr-University Bochum |
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Multi-core SoC Mixed Mode Prototyping Using Synopsys HAPS-70 System
Author(s): Pavel Osipenko, Grigory Khrenov, Grigory Antyufeev, Ivan Averin, Andrey Didenko, Maxim Furseev, Constantine Gurin, Igor Suetinov - Baikal Electronics, Russia |
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Virtual Development on Mixed Abstraction Levels - An Agricultural Vehicle Case Study
Author(s): Matthias Jung, Songlin Piao, Thiyagarajan Purusothaman, Xiao Pan, Christoph Grimm, Karsten Berns, Norbert Wehn - University of Kaiserslautern; Thomas Kuhn - Fraunhofer Institute IESE |
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| B4 - Analog Verification |
Analog/Mixed-signal Data Management with Custom Designer and Cliosoft
Author(s): Thilo Schmidt - Elmos Semiconductor AG |
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| B6 - Digital Verification - AMS, UVM, & Debugging |
Extending New Verification Techniques to Mixed-signal SoCs with VCS AMS
Author(s): Alessandro Valerio, Mauro Scandiuzzo, Pierluigi Daglio - STMicroelectronics; Helene Thibieroz, Massimo Prando, Carlo Borromeo - Synopsys |
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Navigating Your Way Toward UVM Version 1.2
Author(s): John Aynsley, David C. Black, Eileen R. Hickey - Doulos |
