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| User Papers and Presentations |
| A1 - Implementation - Synthesis & Test/Failure Analysis |
ATPG Pattern Generation and Converging the Flow for a Complex Nanometer SoC
Author(s): Siobhan Barry, Ravindra Babu Nayudu - Abilis |
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Transitioning from DFTMAX to DFTMAX Ultra
Author(s): Richard Illman - Dialog Semiconductor |
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| A2 - Implementation - Placement, CTS & Routing |
Applying an IC Compiler Flow to Address the Requirements of Automotive Mixed-Signal Designs (3rd Place - Best Paper)
Author(s): Rainer Kraly - Elmos AG |
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Use of Concurrent Clock and Data Optimization in Hardening Processor Cores to 1GHz
Author(s): Richard White, Andrew Miles - Sondrel Ltd. |
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Using Synopsys Physical Guidance Flow with Design Compiler Graphical and IC Compiler for Achieving Maximum Performance and Minimum Leakage Goals for LEON3 Core-based Designs
Author(s): Alexander Korolkov, Igor Orlovsky, Andrey Veitsel - Topcon Positioning Systems, Russia, Jan Andersson - Aeroflex Gaisler, Feodor Merkelov, Dmitry Radchenko - Synopsys Russia |
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| A4 - Analog Mixed-Signal Verification I |
Analog-on-top AMS Verification - A Practical Approach (Technical Committee Award Honorable Mention)
Author(s): Gernot Koch, Jonathan Bradford - Micronas GmbH |
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Top-Level SoC Power-up Simulation Using XA/VCSMX
Author(s): Haiko Morgenstern, Silvia Strähle, Horst Fischer - Infineon, Matthias Kurz, Yawen Tang - Synopsys GmbH |
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Top-level Verification of HV-CMOS Sensor Chips with FineSim
Author(s): Thomas Desel - Micronas GmbH |
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| A5 - Digital Verification I |
Automotive Microcontroller Peripheral IP Verification: Applying Certitude on SystemC Models (1st Place - Best Paper)
Author(s): Jürgen Hanisch - Robert Bosch GmbH; Florian Letombe - Synopsys |
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Boosting VP and RTL Verification by Leveraging a Reusable UVM Environment
Author(s): Thomas Leitner - Danube Mobile Communications Engineering GmbH & Co KG |
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Reverse Gear: Re-Imagining Randomization Using the VCS Constraint Solver
Author(s): Paul Marriott - Verilab Canada Inc., Jonathan Bromley - Verilab UK Ltd. |
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| A6 - Digital Verification II |
Discrete Real Type Modelling in a Schematic Netlisted Topology
Author(s): Jonathan Bradford - Micronas GmbH |
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Easier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption (Best Paper Award, Technical Committee Award)
Author(s): John Aynsley, Dr. Christoph Sühnel and Dr. David Long - Doulos |
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Leveraging SystemVerilog Object-oriented Programming for Distributed Functional Verification
Author(s): Joachim Geishauser, Alexander Schilling, Dirk Heiswolf, Carmen Klug-Mocanu - Freescale Halbleiter Deutschland GmbH |
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| B2 - Implementation - Design Planning |
Using ICV for Power Network ECO (2nd Place - Best Paper)
Author(s): Steffen Rost - Infineon Technologies, Tobias Buschner - Chipglobe GmbH |
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| B3 - System Design - Prototyping & High-Level Synthesis |
Hardware Prototyping and Software Debugging of Multi-core Architectures
Author(s): Stephanie Friederich, Jan Heisswolf, Jürgen Becker - Karlsruhe Institute of Technology, David May - Technical University of Munich |
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| B4 - Analog Mixed-Signal Verification II |
Experimental Flow for Hard IP Migration Between GLOBALFOUNDRIES 28nm Technologies
Author(s): Ramin Navai, Claudia Kretzschmar, Robert Siegmund, Fulvio Pugliese - GLOBALFOUNDRIES |
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Modelling a 0.45µm HV Technology with HiSIM-HV
Author(s): Kerwin Khu, Reinhard Erwe, Maria Cristina Vecchi, Peter Graf - Micronas GmbH |
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| B5 - Digital Verification III |
Reducing Simulation Runtime of RTL Regressions by VCS, Simulation Environment and Test Bench Optimizations
Author(s): Oksana Shatalova, Vitaly Lotorev - Elvees, Vladimir Litovtchenko - Synopsys GmbH |
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| B6 - UPF Methodology / Advanced STA |
Power Intent Constraints: How Adoption of IEEE Standards Improves our IP and Design Methodology
Author(s): Stuart Riches - ARM |
