• All Products
  • Software Integrity
  • Semiconductor IP
  • Verification
  • Design
  • Silicon Engineering
  • Solutions
  • All Services
  • Software Security
  • Silicon Design
  • Community
  • About Us
Discover + Solutions + Services + Community + About Us SolvNet
Products + All Products + Software Integrity + Semiconductor IP + Verification + Design + Silicon Engineering
Global Sites 日本サイ ト 中文网站

SNUG Germany 2014 Proceedings

2017  |  2016  |  2015  |  2014  |  2013  |  2012

Complete Proceedings

Speeches
Welcome and Keynote
Designing Change – Leveraging Innovation and Collaboration
Author(s): Joachim Kunkel, Senior Vice President and General Manager Solutions Group - Synopsys, Inc.
User Papers and Presentations
A1 - Implementation - Synthesis & Test/Failure Analysis
ATPG Pattern Generation and Converging the Flow for a Complex Nanometer SoC
Author(s): Siobhan Barry, Ravindra Babu Nayudu - Abilis
PaperPresentation

Transitioning from DFTMAX to DFTMAX Ultra
Author(s): Richard Illman - Dialog Semiconductor
PaperPresentation
A2 - Implementation - Placement, CTS & Routing
Applying an IC Compiler Flow to Address the Requirements of Automotive Mixed-Signal Designs (3rd Place - Best Paper)
Author(s): Rainer Kraly - Elmos AG
PaperPresentation

Use of Concurrent Clock and Data Optimization in Hardening Processor Cores to 1GHz
Author(s): Richard White, Andrew Miles - Sondrel Ltd.
PaperPresentation

Using Synopsys Physical Guidance Flow with Design Compiler Graphical and IC Compiler for Achieving Maximum Performance and Minimum Leakage Goals for LEON3 Core-based Designs
Author(s): Alexander Korolkov, Igor Orlovsky, Andrey Veitsel - Topcon Positioning Systems, Russia, Jan Andersson - Aeroflex Gaisler, Feodor Merkelov, Dmitry Radchenko - Synopsys Russia
PaperPresentation
A4 - Analog Mixed-Signal Verification I
Analog-on-top AMS Verification - A Practical Approach (Technical Committee Award Honorable Mention)
Author(s): Gernot Koch, Jonathan Bradford - Micronas GmbH
PaperPresentation

Top-Level SoC Power-up Simulation Using XA/VCSMX
Author(s): Haiko Morgenstern, Silvia Strähle, Horst Fischer - Infineon, Matthias Kurz, Yawen Tang - Synopsys GmbH
PaperPresentation

Top-level Verification of HV-CMOS Sensor Chips with FineSim
Author(s): Thomas Desel - Micronas GmbH
PaperPresentation
A5 - Digital Verification I
Automotive Microcontroller Peripheral IP Verification: Applying Certitude on SystemC Models (1st Place - Best Paper)
Author(s): Jürgen Hanisch - Robert Bosch GmbH; Florian Letombe - Synopsys
PaperPresentation

Boosting VP and RTL Verification by Leveraging a Reusable UVM Environment
Author(s): Thomas Leitner - Danube Mobile Communications Engineering GmbH & Co KG
PaperPresentation

Reverse Gear: Re-Imagining Randomization Using the VCS Constraint Solver
Author(s): Paul Marriott - Verilab Canada Inc., Jonathan Bromley - Verilab UK Ltd.
PaperPresentation
A6 - Digital Verification II
Discrete Real Type Modelling in a Schematic Netlisted Topology
Author(s): Jonathan Bradford - Micronas GmbH
PaperPresentation

Easier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption (Best Paper Award, Technical Committee Award)
Author(s): John Aynsley, Dr. Christoph Sühnel and Dr. David Long - Doulos
PaperPresentation

Leveraging SystemVerilog Object-oriented Programming for Distributed Functional Verification
Author(s): Joachim Geishauser, Alexander Schilling, Dirk Heiswolf, Carmen Klug-Mocanu - Freescale Halbleiter Deutschland GmbH
PaperPresentation
B2 - Implementation - Design Planning
Using ICV for Power Network ECO (2nd Place - Best Paper)
Author(s): Steffen Rost - Infineon Technologies, Tobias Buschner - Chipglobe GmbH
PaperPresentation
B3 - System Design - Prototyping & High-Level Synthesis
Hardware Prototyping and Software Debugging of Multi-core Architectures
Author(s): Stephanie Friederich, Jan Heisswolf, Jürgen Becker - Karlsruhe Institute of Technology, David May - Technical University of Munich
PaperPresentation
B4 - Analog Mixed-Signal Verification II
Experimental Flow for Hard IP Migration Between GLOBALFOUNDRIES 28nm Technologies
Author(s): Ramin Navai, Claudia Kretzschmar, Robert Siegmund, Fulvio Pugliese - GLOBALFOUNDRIES
PaperPresentation

Modelling a 0.45µm HV Technology with HiSIM-HV
Author(s): Kerwin Khu, Reinhard Erwe, Maria Cristina Vecchi, Peter Graf - Micronas GmbH
PaperPresentation
B5 - Digital Verification III
Reducing Simulation Runtime of RTL Regressions by VCS, Simulation Environment and Test Bench Optimizations
Author(s): Oksana Shatalova, Vitaly Lotorev - Elvees, Vladimir Litovtchenko - Synopsys GmbH
PaperPresentation
B6 - UPF Methodology / Advanced STA
Power Intent Constraints: How Adoption of IEEE Standards Improves our IP and Design Methodology
Author(s): Stuart Riches - ARM
PaperPresentation
Tutorials
A1 - Implementation - Synthesis & Test/Failure Analysis
Camelot - A CAD-Navigation Tool, Supporting Failure Analysis for Fault Localization
Author(s): Michael Bruegel (Synopsys GmbH)
Tutorial
B1 - Implementation - Formal Verification
DC Explorer - Quickstart to Logic Synthesis
Author(s): Thorsten Hartmann - Renesas
Presentation

ECO Implementation Assistance and Advanced Debugging Using Formality Ultra
Author(s): Robert Hatt - Synopsys, Inc.
Tutorial
B2 - Implementation - Design Planning
Using Data Flow Analysis for Floorplanning in IC Compiler and DC Explorer
Author(s): Frank De Meersman - Synopsys
Tutorial
B4 - Analog Mixed-Signal Verification II
Utilizing the Latest System Verilog 2012 Enhancements for Mixed-Signal Verification and High-Performance Real Number Modeling
Author(s): Peter Thompson - Synopsys
Tutorial
B5 - Digital Verification III
A Starter's Guide to Using Synopsys Discovery PCIe Verification IP
Author(s): Denis Bussaglia - Synopsys
Tutorial

Debugging Embedded Software Using Verdi HW/SW Debug
Author(s): Jörg Richter - Synopsys
Tutorial
B6 - UPF Methodology / Advanced STA
PrimeTime Advanced ECO
Author(s): Gernot Gall - Synopsys
C1 - Implementation - New Technology
IC Compiler II and the Power of 10x: A Product Walk-through
Author(s): Thomas Andersen - Synopsys
C3 - System Design - IP: Embedded ARC Cores in Automotive
Easing the Road to ISO 26262 Compliance with the ARC EM SEP Processor Core
Author(s): Fergus Casey - Synopsys
Tutorial
C5 - Verification - New Technology
Verification Vision
Author(s): Arturo Salz - Synopsys
Workshop
C4 - Custom Routing
Galaxy Custom Router Workshop
Author(s): Chris Shaw - Synopsys
Tutorial
Combo
A3 - System Design - Processor Design
Programmability – Enabler for Increased IP Reuse
Author(s): Dr. Gert Goossens - Synopsys; Dr. Liesbet Van der Perre - IMEC
Tutorial Tutorial
B3 - System Design - Prototyping & High-Level Synthesis
Implementing Highly Efficient Audio IP Cores Using an HLS Approach
Author(s): Philipp Jacobsohn - Synopsys, Mirko Skopp - Rohde & Schwarz
Tutorial
Silicon Valley 2017 Keynote

Dr. Peter Stone on “Learning and Multiagent Reasoning for Autonomous Robots”

Contact the SNUG Operations team for proceedings prior to 2012

View All SNUG Proceedings
Contact Us

Platinum Sponsors:

Arm
GLOBALFOUNDRIES
Samsung
tsmc
Related Items