2016论文集
技术委员会获奖论文
一等奖
Application of ICC2 timing budgeting for large scale hierarchical design
二等奖
An easy way to run gate level simulation for accurate power estimation
三等奖
Ease of Use for DRC Checking with IC Validator
最佳演讲论文
An easy way to run gate level simulation for accurate power estimation
入围论文
使用HAPS-72系统基于64位四核ARM Cortex-A53处理器SoC的软硬件协同验证
Develop Intelligent Apps to Speed up Huge Amount of Results Analysis Automatically with VCLP API
Appling Advanced DFT Method Share-Codec IO to Pin Limited Design
A brand new building block for verification
Designing a BIT-ASIP adopting Synopsys ASIP Designer
An easy way to run gate level simulation for accurate power estimation
TIO-A more efficient way to speed up top level timing closure during ECO
Unified Compile and Debug - Verification Compiler Boosting Performance &Efficiency
Apply Property Checking in Sub-block Verification Using VC Formal
Ease of Use for DRC Checking with IC Validator
Advance On-Chip Variation(AOCV) Characterization With SiliconSmart
NEXT GENERATION PCIE BASED ENTERPRISE SSD SOLUTION USING ARC PROCESSORS
Application of ICC2 timing budgeting for large scale hierarchical design
Idenity Holes and Improve Testbench Quality with Native Certitude
An Efficient SoC Connectivity Checking Using VC Apps
Design and Verification of Large Size High Resolution AMOLED TV
Achieving Faster Results Approach With Synopsys DCT/DCG
用Synopsys的AMS完整流程高效地完成16nm FinFET工艺的设计
Advanced Node FinFet PnR QoR improvement based on AWE and net pattern research
Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP
Low Power Verification of the complex design
Liberty characterization and validation with SiliconSmart
Clock Domain Crossing Checks of Giant Scale Circuit Based on SpyGlass CDC
Multi-FPGA Prototyping Systems for Smart-TV with HAPS and ProtoCompiler
IC Compiler II exploration in 14nm process
Method and Analysis of Power Optimization by PT in 14nm Process
Automatic H-tree Based Multisource Clock Tree Synthesis (AHB-MSCTS) Design
Latch-based CPU Prototyping with HAPS Platform
