技术委员会获奖论文
一等奖
PCIe Test suite: A powerful capsule for an effective fast paced verification
二等奖
Implementation Flow with Multi-bit Banking
三等奖
Dynamic Power Optimization Strategy for Different Designs
最佳演讲论文
Comprehensive methods to resolve advanced nodes custom layout density issue with Laker
Development of an accelerated and comprehensive MIPI CSI2DSI verification environment
入围论文文
Power Analysis Visualization with Verdi VC Apps NPI
Advanced Clock Domain Crossing Checks for FPGA Design Using Static Verification
An Efficient Way to Verify The Graphic Image Processing Circuit
Concurrent Clock and Data Optimization
Clock Tree Implementation Strategies for 28nm Cortex-A7 core
Dynamic IR Signoff Using PrimeRail GenII
Evaluate power gate cells Insertion Style Using PrimeRail
Generating Cell Internal Based Patterns and Diagnosing Cell Internal Defects with Cell-Aware ATPG
Implementation Flow with Mutli-bit Banking
Improve designer productivity and project quality with Lynx Design System
Low Power Design Technique Using Multibit Register Mapping in DCG
Low-latency and Timing-aware Multi-point Clock Tree Synthesis
Research and Application of Multi-core Technology in SOC Verification
A method to avoid the dont_touch net attribute derived from ICC always-on synthesis
Faster TAT ? Hierarchical timing closure using HyperScale
Using PrimeTime HyperScale to accelerate large scale hierarchical design timing closure
Low power verification based on UPF coverage
Strategies To Improve QoR on FinFETs Design
The Application of IEEE1500 Core Wrapper in ULSI Design
Using VC-STATIC LP for Successful Tapeouts at AMD
VC Apps based SoC System Level Connection Sign-off Flow
Verification for usb in chip-level environment with VC VIP for USB
Application of Package-Driven Flip-Chip Flow in Module design
