最佳论文：
A Methodology of Multi-Step Synthesis and Formal Check for Retiming Design
优秀论文：
An Efficient Design Performance Analysis Method Using Verdi Interoperability App
Module Level Resynthesis With Physical Information to Resolve Congestion
ZeBu Emulator Multi-Core DSP and SoC System Verification
入选论文：
20-nm and Beyond Physical Design Implementation
A Flow for Back-Annotating Physical Design Constraints
Achieving High-Quality At_Speed Scan Pattern Using Tetramax
Advanced Timing Fix Skills using PrimeTime
An Effective Way to Reduce Congestion Through Hierarchical Routing Channel and Flat Extraction
An Efficient Way to Optimize Leakage Power Under MCMM
ARM Cortex-A7 Implementation With Synopsys Flow
DFT Implementation for Ultra-Large Scale Circuit
Efficient Embedded Software Debug
Improve Debug Efficiency With VIA-LogViewer and VIA Programming Platform
NanoTime Timing Analysis Accelerating Methods
Practical Coverage Flow in SOC Verification
Reducing Test Cost While Improving Test Quality Using Advanced DFT Method DFTMAX-ULTRA and TMAX
Self-Adapting Verification Environment for Parameterized IP with AMBA SVT VIP
Synthesis Strategies for High-Performance Design in Design Compiler
Using Verdi NPI in SOC Top Connection Checking
VSI-LP-Based Automatic Generation Solution to Optimize Low-Power UPF Design
