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2017 论文集
技术委员会获奖论文
一等奖
Excellent Trade-off on Several Low Power Methods for Retiming Pipeline
二等奖
Exploration of Relative Placement Groups for Clock Sinks with ICC II
Improving Verification Productivity with Partition Compile Technology
三等奖
An Efficient Method to Enhance Verification Environment via Certitude
Methods to Prevent IR-Drop at Early Stage of Design Implementation
Based On Formal Tools to Create Exclusion File
最佳演讲论文
Hierarchical Multi-mode DFT Implementation for Wrapped Encrypted IP
入围论文
Implementation of Stuck at and Transition fault test using LogicBIST with user defined OCC
Better Efficient AOCV Usage Approach With Synopsys EDA TOOL
An efficient method to enhance verification environment via Certitude
Functional Verification with FSM Stimulus Generator for Effective Closure
Interconnection logic testing with Tetramax
Methodology for RTL DFT Violation and Coverage Analysis
Scan input sharing with Tetramax
Customized Finesim+VCS Integration Flow with Custom Compiler
Finesim in high performance ADC design flow
Using The Cell-Aware Test Flow For ATPG Pattern Generation And Diagnosis
Unified Verification Framework Automation and Test Standardization with UVM
Using ICC2 to assign pins for channel-less large scale design
Achieve better performance of timing budget flow with IC-Complier II
The Z01X application of defect coverage evaluation in Digtal-analog Mixed chip
A fast Synthesis Flow which can automatically improve and perfect real physical constraints
Mutation_coverage's application in formal by certitude
A case study – Formal Proof for ECC Logic by VC Formal
MTBF flow based on SpyGlass CDC
Hierarchical Multi-mode DFT Implementation for Wrapped Encrypted IP
用CCK工具来提高Flash IP设计的可靠性(Enhance Flash IP Design Reliability by CCK Simulation)
An Application Note about Improving Timing Correlation between ICC2 and PT
Exploration of Relative Placement Groups for Clock Sinks with ICC II
Methods to prevent ir-drop at early stage of design implementation
Using SpyGlass Power to optimize power at RTL level
Based On Formal Tools to Create Exclusion File
Improving Verification Productivity with Partition Compile Technology
Backdoor in FPGA prototyping based on Synopsys HAPS platform
Excellent Trade-off on Several Low Power Methods for Retiming Pipeline
Realize low-pin & low-cost & low-power DFT design using DFTMAX-Ultra
Achieving Signoff TAT and Resource Usage Goals with HyperScale
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