Conference at a Glance

SNUG Canada | October, 1, 2015

Thursday, October 1, 2015

 Time

Description 

8:00-9:00 Registration and Breakfast
9:00-10:30 Welcome: Costas Conistis, Synopsys & Technical Chair Paul Lungu, Ciena

Keynote Address: Silicon to Software - 'Shift Left'
Chi-Foon Chan, President and co-CEO - Synopsys
10:30-10:45 Break
 

Verification

Implementation I

Implementation II

10:45-12:15

A1 - User Session - Testbench Techniques with UVM

Verifying C++ Firmware Sequences in UVM Environment
Best Presentation - 3rd Place

Replacing Hardcoded Register Values with Hardcore Abstraction

RESSL UVM Sequences to the Mat

A2 - User & Tutorial Session - PrimeTime PX and Large Scale Design STA

Gaining Confidence in Your Publicized Power Numbers

Large Scale Design STA - Hierarchical or Flat, Distributed or Single Machine - Which Way to Go for Timing Signoff?

A3 - Panel Session - IC Compiler II

Unleashing the Power of IC Compiler II - User Experiences

12:15-1:15 Lunch
 

Verification

Implementation I

Implementation II

1:15-3:15

B1 - User Session - Speed Up Your Simulation

Architecting Your Way to Acceleration in UVM
Technical Committee Award Winner Technical Committee Award Winner

SVAs in IP - The Holy Grail or the Holy Snail

Method to Partition Your Gate Simulation Debug
Best Presentation - 1st Place

B2 - Tutorial Session - Achieving Optimal QoR with Design Compiler

Achieving Optimal Quality of Results Faster with Design Compiler

B3 - User & Tutorial Session - IC Compiler & PrimeTime SI

Experiences Using PrimeTime Physically-Aware ECO Technology

Script Based DDR Data Bus Balancing Using IC Compiler
Best Presentation - 2nd Place

Using Data Flow Analysis for Floorplanning

3:15-3:30 Break
 

Verification

Implementation I

Implementation II

3:30-5:00

C1 - Tutorial Session - Coverage Closure & Advanced Debug

Speed Up Coverage Closure with VC FCA & Echo

Advanced Protocol Debug with Verdi3 2015.09

C2 - User & Tutorial Session - SerDes Integration and RTL Power Estimation

Physical and Timing Aspects of Synopsys DesignWare Enterprise 12G SerDes Integration

Using SpyGlass to Monitor and Reduce Power in Your Design

C3 - Tutorial Session - IC Compiler Update

IC Compiler's Latest 2015.06 Release Delivers Significant Performance Power Area (PPA) Improvements and Faster Closure on Emerging and Established Nodes

5:00-6:00 SNUG Pub and Awards Presentation