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SNUG Boston 2015 Proceedings

2018 | 2017 | 2015 | 2014 | 2013 

Complete Proceedings

Speeches
Keynote
Silicon to Software: Shift Left
Author(s): Deirdre Hanford, Executive Vice President, Customer Engagement - Synopsys
User Papers and Presentations
A1 User Session - Deploying Formal Verification
Formal Verification of a Multistage Arbiter
Author(s): Shahid Ikram, Craig Barner, John Sweeney, and Jim Ellis - Cavium; Bill Dufresne - Synopsys
PaperPresentation

From Specification to Complete RTL Verification Using Formal Methodology
Author(s): Suckheui Chung - AMD
PaperPresentation
A2 User Session - Adaptability of UVM in Complex Environments
Customization of RAL Adapters and Predictors in UVM 1.2
Author(s): Steven K. Sherman - AMD
PaperPresentationSession Recording

Customizing UVM Report Server (UVM 1.1d, UVM 1.2)
Author(s): Kaushal Modi - Analog Devices
PaperPresentation

Lies My Teacher Told Me About The UVM - Basic Stimulus (Best Presentation - 1st Place)
Author(s): Justin Refice - NVIDIA
PaperPresentationSession Recording
A3 User Session - Optimizing Your Verification Environment
Developing C++ Testbench Components Using UVM Phase and Agent Concepts
Author(s): JinHaeng Cho, Scot Hildebrandt - NVIDIA
PaperPresentationSession Recording

Using Certitude Efficiently
Author(s): Shahid Ikram, Craig Barner, Joseph D'Errico, and Jim Ellis - Cavium; Marty Rowe - Synopsys
PaperPresentation
B2 Tutorial Session - Synthesis & Power Analysis
Clock Design Challenges in a Large, Low-Power, High-Speed Signal Processing Design (Best Presentation - 3rd Place)
Author(s): Rishi Yadav, Nimit Nguansiri - The MITRE Corporation
PaperPresentation

UPF-Based Synthesis Flow for Complex Mixed Signal IP Blocks (Technical Committee Award)
Author(s):
PaperPresentation
B3 User Session - Technical Committee Best Papers from SNUG Europe
MTCMOS Based Low Power Implementation in GLOBALFOUNDRIES 28nm Process Using UPF2.0 - A Case Study
Author(s): Ramin Navai - Synopsys; Farid Labib - GLOBALFOUNDRIES
PaperPresentationSession Recording
C1 Tutorial & User Session - ICC and Design Planning
DFA One Step Further - Quicker Floorplan Convergence with Topology Driven Flylines (Best Presentation - 2nd Place)
Author(s):
PaperPresentation
E2 Tutorial & User Session - Layout & Simulation Productivity Improvements
Navigating the SPICE Continuum
Author(s): David W. Winston - IBM
PaperPresentationSession Recording
F1 User Session - System Integration and Design
AMBA Interconnect Design Flow Automation
Author(s): Tom Ajamian - Analog Devices
PaperPresentation

PDSparc - A Drop-In Replacement for LEON3 Written Using Synopsys Processor Designer
Author(s): David Whelihan, Ph.D., Kate Thurmer - MIT Lincoln Laboratory
PaperPresentation
F3 User Session - HW Emulation
Enabling Greater Reliability, Scalability, and Flexibility of GPU Emulation with a Hybrid Virtual Machine Based Approach
Author(s): Alex Starr - AMD
PaperPresentationSession Recording
Publication Only
Publish Only
Checking Typos in Simulation Command Line Plusargs
Author(s): Thinh Ngo - Broadcom
Publish Only
Tutorials
B1 Tutorial Session - Synthesis
Achieving Optimal Quality of Results Faster with Design Compiler
Author(s): Tom Wilderotter - Synopsys
TutorialVideo

What's New with Synthesis from R&D's Perspective
Author(s): Janet Olson - Synopsys
TutorialVideo
C1 Tutorial & User Session - ICC and Design Planning
ICC 2015.06 Update - Highlighting the Latest Capabilities
Author(s): Dave Power - Synopsys
TutorialVideo
C2 Tutorial Session - ICC II and ARM Place & Route
High-Performance, Energy-Efficient Implementation of the ARM Cortex-A72 Processor Using Synopsys IC Compiler and IC Compiler II Place-and-Route Systems
Author(s): Joe Walston - Synopsys
TutorialVideo

ICC II Marketing and R&D Update
Author(s): Stelios Diamantidis, Henry Sheng - Synopsys

ICC II Technical Highlights and User Experience
Author(s): Joe Varghese - Synopsys; Zhong Chen, Bill Stysiack, Najam Zaman - Cavium
TutorialVideo
C3 User & Tutorial Session - ICC II
Getting Productive in the ICC II GUI
Author(s): Dan Guilin - Synopsys
TutorialVideo
D1 Tutorial Session - Scan Compression
Understanding Compression - Past, Present, and Future
Author(s): Rohit Kapur - Synopsys
TutorialVideo
D2 Tutorial Session - Technology
Auto LBIST
Author(s): Don Skinner - Synopsys
Tutorial

Lowering DPPM through Advanced Fault Models
Author(s): Don Skinner - Synopsys
Tutorial

SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System
Author(s): Mike Ricchetti - Synopsys
TutorialVideo
D3 Tutorial Session - Introducing Synopsys SpyGlass
Introduction to SpyGlass DFT ADV
Author(s): Al Joseph - Synopsys
TutorialVideo

Introduction to SpyGlass Power
Author(s): Al Joseph - Synopsys
TutorialVideo

Introduction to Synopsys SpyGlass
Author(s): Al Joseph - Synopsys
TutorialVideo
E2 Tutorial & User Session - Layout & Simulation Productivity Improvements
Getting to Simulation Results Faster with StarRC
Author(s): Al Blais - Syopsys
TutorialVideo

Need to Simulate SPICE Netlists? Have I Got a GUI for You!
Author(s): Dave Chou - Synopsys
TutorialVideo
E3 User & Tutorial Session - Efficient Transistor Level implementation
Achieving Productive Custom Layout When Using FinFET Devices
Author(s): Nicolas Regis – Synopsys
TutorialVideo
F2 Tutorial Session - FPGA Prototyping and Design
Incorporating UPF Specifications and Equivalence Checking into your FPGA Prototype
Author(s): Steven Gercken - Synopsys
TutorialVideo

Multi-FPGA Prototyping of Over 1.5 Billion ASIC Gates
Author(s): Troy Scott - Synopsys
TutorialVideo

Recent Developments in High Reliability Design Techniques for FPGA
Author(s): Carl Cleaver - Synopsys
TutorialVideo
Panel Presentation
E1 Panel & Demo Session - VCS AMS Verification
Tackle Mixed-signal Verification Challenges From Block-level Design to Complex SoCs With VCS AMS
Author(s): John Brennan - Cavium; Helene Thibieroz, Warren Anderson - Synopsys
Tutorial
Demo
E1 Panel & Demo Session - VCS AMS Verification

Demonstration of New VCS AMS Concepts
Author(s): Maureen Ladd - Synopsys
TutorialVideo
User Presentation
B2 Tutorial Session - Synthesis & Power Analysis
Accurate Time-Based Power Analysis on a Complex Design Using RTL Simulation Activity
Author(s): James Lee - Qualcomm
Presentation
B3 User Session - Technical Committee Best Papers from SNUG Europe
Advanced Synthesis Technique Using Target Library Subset
Author(s): Laurent Besson - STMicroelectronics
PresentationVideo
C3 User & Tutorial Session - ICC II
Investigating the Next Generation Place and Route Tool
Author(s):
Presentation
D1 Tutorial Session - Scan Compression
Achieving High Compression Ratios with Cell-Constrained Designs Using DFTMAX Ultra
Author(s): Anand Gangwar - Synopsys; Kalyana Kantipudi - Altera
Presentation
E3 User & Tutorial Session - Efficient Transistor Level implementation
EDA Flow for a Power-Efficient Microprocessor Using iPDK Created from Non-Interoperable oaPDK and Modified Synthesis to Support Asynchronous Logic
Author(s): Bill Ellersick - Analog Circuit Works; Dylan Hand - Reduced Energy Microsystems; Peter Berell - University of Southern California
PresentationVideo
F3 User Session - HW Emulation
Multi-Platform Continuum: ZeBu to Post-Silicon …. and Back
Author(s): Al Czamara - Test Evolution
TutorialVideo

Call for Papers Open
11/7/18 - 12/21/18

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