|
User Papers and Presentations |
A1 User Session - Deploying Formal Verification |
Formal Verification of a Multistage Arbiter Author(s): Shahid Ikram, Craig Barner, John Sweeney, and Jim Ellis - Cavium; Bill Dufresne - Synopsys |
|
From Specification to Complete RTL Verification Using Formal Methodology Author(s): Suckheui Chung - AMD |
|
A2 User Session - Adaptability of UVM in Complex Environments |
Customization of RAL Adapters and Predictors in UVM 1.2 Author(s): Steven K. Sherman - AMD |
|
Customizing UVM Report Server (UVM 1.1d, UVM 1.2) Author(s): Kaushal Modi - Analog Devices |
|
Lies My Teacher Told Me About The UVM - Basic Stimulus (Best Presentation - 1st Place) Author(s): Justin Refice - NVIDIA |
|
A3 User Session - Optimizing Your Verification Environment |
Developing C++ Testbench Components Using UVM Phase and Agent Concepts Author(s): JinHaeng Cho, Scot Hildebrandt - NVIDIA |
|
Using Certitude Efficiently Author(s): Shahid Ikram, Craig Barner, Joseph D'Errico, and Jim Ellis - Cavium; Marty Rowe - Synopsys |
|
B2 Tutorial Session - Synthesis & Power Analysis |
Clock Design Challenges in a Large, Low-Power, High-Speed Signal Processing Design (Best Presentation - 3rd Place) Author(s): Rishi Yadav, Nimit Nguansiri - The MITRE Corporation |
|
UPF-Based Synthesis Flow for Complex Mixed Signal IP Blocks (Technical Committee Award) Author(s): |
|
B3 User Session - Technical Committee Best Papers from SNUG Europe |
MTCMOS Based Low Power Implementation in GLOBALFOUNDRIES 28nm Process Using UPF2.0 - A Case Study Author(s): Ramin Navai - Synopsys; Farid Labib - GLOBALFOUNDRIES |
|
C1 Tutorial & User Session - ICC and Design Planning |
DFA One Step Further - Quicker Floorplan Convergence with Topology Driven Flylines (Best Presentation - 2nd Place) Author(s): |
|
E2 Tutorial & User Session - Layout & Simulation Productivity Improvements |
Navigating the SPICE Continuum Author(s): David W. Winston - IBM |
|
F1 User Session - System Integration and Design |
AMBA Interconnect Design Flow Automation Author(s): Tom Ajamian - Analog Devices |
|
PDSparc - A Drop-In Replacement for LEON3 Written Using Synopsys Processor Designer Author(s): David Whelihan, Ph.D., Kate Thurmer - MIT Lincoln Laboratory |
|
F3 User Session - HW Emulation |
Enabling Greater Reliability, Scalability, and Flexibility of GPU Emulation with a Hybrid Virtual Machine Based Approach Author(s): Alex Starr - AMD |