|
| User Papers and Presentations |
| A1 User Session - Advanced Verification Technology Part 1 |
Architecturally Speaking, Are We Cool? Effectiveness of Qualifying C/C++ Hardware Model and Simulator Environment Using Certitude C++
Author(s): A Gutmann, John Hayden, David Brownell - Analog Devices; Marty Rowe – Synopsys |
|
Dual Core SoC Debug with Synopsys Hardware Software Debug Tool
Author(s): A. Mark Jesensky, Andy Sha - Analog Devices |
|
Verdi - Embedded Software Debug
Author(s): Dan Grabowski - NVIDIA; Alex Wakefield - Synopsys |
|
| A2 User-Tutorial & Tutorial Session - Advanced Verification Technology Part 2 |
Formal Verification of Debug Bus Connectivity: A Formal App Case Study
Author(s): Oleg Petlin, Andrew Mullen - Advanced Micro Devices; Xiaolin Chen - Synopsys |
|
| A3 User Session - Advanced UVM Techniques |
Stateful Sequence Item and Automatic UVM Testbench Generation
Author(s): Jie Ding, Wen-hsing Chen - Qualcomm |
|
Taming UVM 1.1d RAL in a Multi-Interface, Multi-Mode Environment (2nd Place - Best Presentation)
Author(s): Steve Sherman - AMD |
|
| C2 User & Tutorial Session - Improving Design Productivity |
Addressing Custom DFM Rules and Related DRC Violations with In-Design ICC-ICV-ADR Flow
Author(s): David Rhein - Microsemi Corporation; Darin Heckendorn - Synopsys |
|
Reducing Cell Placement Congestion Using Targeted Pattern Halos (Best Paper Award, Technical Committee Award)
Author(s): |
|
| C3 User & Tutorial Session - Advanced Capabilities of PrimeTime |
Total Power Optimization within PrimeTime-SI for FinFET Technology
Author(s): Bruce Zahn - Avago Technologies |
|
| D1 User Session - Advanced Test Methodologies |
At-Speed Scan Exceptions Based on Functional Slack Reports (1st Place - Best Presentation)
Author(s): Michelle Vallabhanath - Avago Technologies |
|
| E1 User Session - Advanced Technology Methodology |
Challenges of FINFET Implementation in Dual Hierarchy Flow
Author(s): Arnie Baizley, Mike Gambero - IBM; Kevin Brelsford, Jitendra Lagu - Synopsys |
|
Waiving DRC Errors using Pattern Matching (3rd Place - Best Presentation)
Author(s): Pierre Bouchard - IBM; Kevin Brelsford, Jitendra Lagu - Synopsys |
|
| E2 User Session - Custom Analysis |
An Efficient Method for Accounting for Local IR Drop in Advanced Technology Nodes
Author(s): John Faricelli, Wei Huang Zhu, Yegor Puzanov - Advanced Micro Devices |
|
Cell-Based Construction of Mixed-Signal Systems Using Co-Design Flow of IC Compiler and Custom Designer - A Digital PLL Example
Author(s): Sigang Ryu, Jaeha Kim - Seoul National University |
|
Parasitic Extraction Challenges in Enablement
Author(s): Srilata Raman, Cole Zemke - IBM |
|
| F1 User & Tutorial Session: System Emulation Validation Part 1 |
Test IP: Bringing the Tools and Methodology from Pre-Silicon Verification to Post-Silicon Validation
Author(s): Al Czamara, Richard Proto, Paul Tomashevskyi - Test Evolution |
|
| F2 User Session - System Emulation Validation Part 2 |
Successful Application of System Level Emulation
Author(s): |
