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SNUG Boston 2014 Proceedings

2019 | 2018 | 2017 | 2015 | 2014

Complete Proceedings

User Papers and Presentations
A1 User Session - Advanced Verification Technology Part 1
Architecturally Speaking, Are We Cool? Effectiveness of Qualifying C/C++ Hardware Model and Simulator Environment Using Certitude C++
Author(s): A Gutmann, John Hayden, David Brownell - Analog Devices; Marty Rowe – Synopsys
PaperPresentation

Dual Core SoC Debug with Synopsys Hardware Software Debug Tool
Author(s): A. Mark Jesensky, Andy Sha - Analog Devices
PaperPresentation

Verdi - Embedded Software Debug
Author(s): Dan Grabowski - NVIDIA; Alex Wakefield - Synopsys
PaperPresentation
A2 User-Tutorial & Tutorial Session - Advanced Verification Technology Part 2
Formal Verification of Debug Bus Connectivity: A Formal App Case Study
Author(s): Oleg Petlin, Andrew Mullen - Advanced Micro Devices; Xiaolin Chen - Synopsys
PaperPresentation
A3 User Session - Advanced UVM Techniques
Stateful Sequence Item and Automatic UVM Testbench Generation
Author(s): Jie Ding, Wen-hsing Chen - Qualcomm
PaperPresentation

Taming UVM 1.1d RAL in a Multi-Interface, Multi-Mode Environment (2nd Place - Best Presentation)
Author(s): Steve Sherman - AMD
PaperPresentation
C2 User & Tutorial Session - Improving Design Productivity
Addressing Custom DFM Rules and Related DRC Violations with In-Design ICC-ICV-ADR Flow
Author(s): David Rhein - Microsemi Corporation; Darin Heckendorn - Synopsys
PaperPresentation

Reducing Cell Placement Congestion Using Targeted Pattern Halos (Best Paper Award, Technical Committee Award)
Author(s):
PaperPresentation
C3 User & Tutorial Session - Advanced Capabilities of PrimeTime
Total Power Optimization within PrimeTime-SI for FinFET Technology
Author(s): Bruce Zahn - Avago Technologies
PaperPresentation
D1 User Session - Advanced Test Methodologies
At-Speed Scan Exceptions Based on Functional Slack Reports (1st Place - Best Presentation)
Author(s): Michelle Vallabhanath - Avago Technologies
PaperPresentation
E1 User Session - Advanced Technology Methodology
Challenges of FINFET Implementation in Dual Hierarchy Flow
Author(s): Arnie Baizley, Mike Gambero - IBM; Kevin Brelsford, Jitendra Lagu - Synopsys
PaperPresentation

Waiving DRC Errors using Pattern Matching (3rd Place - Best Presentation)
Author(s): Pierre Bouchard - IBM; Kevin Brelsford, Jitendra Lagu - Synopsys
PaperPresentation
E2 User Session - Custom Analysis
An Efficient Method for Accounting for Local IR Drop in Advanced Technology Nodes
Author(s): John Faricelli, Wei Huang Zhu, Yegor Puzanov - Advanced Micro Devices
PaperPresentation

Cell-Based Construction of Mixed-Signal Systems Using Co-Design Flow of IC Compiler and Custom Designer - A Digital PLL Example
Author(s): Sigang Ryu, Jaeha Kim - Seoul National University
PaperPresentation

Parasitic Extraction Challenges in Enablement
Author(s): Srilata Raman, Cole Zemke - IBM
PaperPresentation
F1 User & Tutorial Session: System Emulation Validation Part 1
Test IP: Bringing the Tools and Methodology from Pre-Silicon Verification to Post-Silicon Validation
Author(s): Al Czamara, Richard Proto, Paul Tomashevskyi - Test Evolution
PaperPresentation
F2 User Session - System Emulation Validation Part 2
Successful Application of System Level Emulation
Author(s):
PaperPresentation
Publication Only
Publish Only
Efficient Gbit/s Data Transceivers Designed for Verification and SoC Integration
Author(s): Dr. William Ellersick - Analog Circuit Works
Publish Only

Overcome SoC Integration Challenges with ASIC IPs by Utilizing DC Features and Beyond
Author(s): Anne Yue, Guy Wadsworth - Synapse Design; Frederic Raynal, Don Sanders - Audience; Lawrence Esker, David Zbasnik - ViaSat
Publish Only
Tutorials
A2 User-Tutorial & Tutorial Session - Advanced Verification Technology Part 2
Verification Compiler - Rethinking Verification
Author(s): Mike Lucente - Synopsys
B1 Tutorial & User-Tutorial Session - Formality
Functional ECOs Made Easier with Formality Ultra
Author(s): Erin Hatch - Synopsys
Tutorial
B2 Tutorial, User & Demo Session - Synthesis
Design Compiler 2014.09 Highlights
Author(s): Janet Olson - Synopsys
Tutorial
B3 Tutorial Session - Low Power
What Every Leakage-Concerned Engineer Wants to Know (And Never Tires of Asking Us)
Author(s): John Geremia - Synopsys
Tutorial

What's New in VC LP Advanced Low Power Static Checking
Author(s): Tushar Parikh - Synopsys
Tutorial
C1 Tutorial Session - The Future of Place and Route
IC Compiler II and the Power of 10x - A Product Walk-Through
Author(s): Neeraj Kaul, Stelios Diamantidis - Synopsys

User Experience: Accelerating Designs to Market With IC Compiler II
Author(s): Barry Turner - Synopsys
Tutorial
C2 User & Tutorial Session - Improving Design Productivity
IC Compiler J-2014.09 Release Highlights
Author(s): Dave Power - Synopsys
Tutorial
C3 User & Tutorial Session - Advanced Capabilities of PrimeTime
PrimeTime ECO - Now Physically Aware
Author(s): Paul Lamers - Synopsys
Presentation
D2 Tutorial Session - Improving Test
Low DPPM Testing for All Process Nodes and FinFETs
Author(s): Adam Cron - Synopsys
Tutorial

Reducing the Time, Effort and Cost of Quality SoC Testing
Author(s): Adam Cron - Synopsys
Tutorial
F1 User & Tutorial Session: System Emulation Validation Part 1
Integrating Synphony Model Compiler's High-Level Algorithm Synthesis with HAPS Prototyping Systems
Author(s): Carl Cleaver - Synopsys
Tutorial
F2 User Session - System Emulation Validation Part 2
Using Synopsys VDKs for Developing UEFI and Linux Drivers for Synopsys DesignWare IP Interfaces and ARMv8 Processors
Author(s): Aditya Goswami - Synopsys
Tutorial

Verification of SoC Designs with ZeBu HW Emulator
Author(s): Peter Calabrese - Synopsys
Tutorial
F3 User-tutorial & Tutorial Session - FPGA Implementation and Debug
Integrating Siloti into Live FPGA Debug
Author(s): Kris Dobecki - Synopsys
Tutorial
Demo
B2 Tutorial, User & Demo Session - Synthesis
RTL Analysis and Cross Probing Demonstration
Author(s): Craig Maiman - Synopsys
Workshop
D3 Workshop - Enabling SoC Implementation
IC Compiler and Galaxy Custom Router Workshop
Author(s): Chris Shaw - Synopsys
User Presentation
A2 User-Tutorial & Tutorial Session - Advanced Verification Technology Part 2
Leveraging VCS Xprop for Quick Resolution of X Uncertainty Issues
Author(s): Vito Greco - Analog Devices
Presentation
B1 Tutorial & User-Tutorial Session - Formality
Formality ECO Saving the Day, or at Least the Schedule
Author(s): Ranjith Hallur - Cavium
Presentation
B2 Tutorial, User & Demo Session - Synthesis
DC Explorer - Quickstart to Logic Synthesis
Author(s): Thorsten Hartmann - Renesas Electronics Europe GmbH; Pervinder Trehan - Synopsys
Presentation
D1 User Session - Advanced Test Methodologies
Internal Cell Fault Isolation for 20nm Standard Cell Libraries
Author(s): David Corrigan - GLOBALFOUNDRIES; Frank Nolting, Lori Schramm - Synopsys
Presentation
E3 User Session - Advanced Design Methodology
Synchronization and Metastability
Author(s): Steve Golson - Trilobyte Systems
Presentation
F3 User-tutorial & Tutorial Session - FPGA Implementation and Debug
Getting Results with Xilinx’s Stacked Silicon Interconnect Devices
Author(s): Tim Blanchard - Xilinx
Presentation
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