Conference at a Glance

SNUG Boston | September 24, 2015

Thursday, September 24, 2015



8:30-9:15 Registration and Breakfast
9:15-10:30 Welcome: Mark Sprague, SNUG Boston Technical Chair - Teradyne

Keynote: Silicon to Software: Shift Left
Deirdre Hanford, Executive Vice President, Customer Engagement - Synopsys

10:30-10:45 Break


Frontend Implementation

Physical Design



System Integration, Emulation, and FPGA Prototyping


A1 User Session - Deploying Formal Verification

From Specification to Complete RTL Verification Using Formal Methodology

Formal Verification of a Multistage Arbiter

B1 Tutorial Session - Synthesis

What's New with Synthesis from R&D's Perspective

Achieving Optimal Quality of Results Faster with Design Compiler

C1 Tutorial & User Session - ICC and Design Planning

ICC 2015.06 Update - Highlighting the Latest Capabilities

DFA One Step Further - Quicker Floorplan Convergence with Topology Driven Flylines
Best Presentation - 2nd Place

D1 Tutorial Session - Scan Compression

Understanding Compression - Past, Present, and Future

Achieving High Compression Ratios with Cell-Constrained Designs Using DFTMAX Ultra

E1 Panel & Demo Session - VCS AMS Verification

Tackle Mixed-signal Verification Challenges From Block-level Design to Complex SoCs With VCS AMS

Demonstration of New VCS AMS Concepts

F1 User Session - System Integration and Design

PDSparc - A Drop-In Replacement for LEON3 Written Using Synopsys Processor Designer

AMBA Interconnect Design Flow Automation

12:15-1:15 Lunch


Frontend Implementation

Physical Design



System Integration, Emulation, and FPGA Prototyping


A2 User Session - Adaptability of UVM in Complex Environments

Customization of RAL Adapters and Predictors in UVM 1.2

Customizing UVM Report Server (UVM 1.1d, UVM 1.2)

Lies My Teacher Told Me About The UVM - Basic Stimulus
Best Presentation - 1st Place

B2 Tutorial Session - Synthesis & Power Analysis

UPF-Based Synthesis Flow for Complex Mixed Signal IP Blocks
Technical Committee Award Winner Best Paper Award, Technical Committee Award Winner

Clock Design Challenges in a Large, Low-Power, High-Speed Signal Processing Design
Best Presentation - 3rd Place

Accurate Time-Based Power Analysis on a Complex Design Using RTL Simulation Activity

C2 Tutorial Session - ICC II and ARM Place & Route

ICC II Marketing and R&D Update

ICC II Technical Highlights and User Experience

High-Performance, Energy-Efficient Implementation of the ARM Cortex-A72 Processor Using Synopsys IC Compiler and IC Compiler II Place-and-Route Systems

D2 Tutorial Session - Technology

Lowering DPPM through Advanced Fault Models


SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System

E2 Tutorial & User Session - Layout & Simulation Productivity Improvements

Getting to Simulation Results Faster with StarRC

Navigating the SPICE Continuum

Need to Simulate SPICE Netlists? Have I Got a GUI for You!

F2 Tutorial Session - FPGA Prototyping and Design

Recent Developments in High Reliability Design Techniques for FPGA

Incorporating UPF Specifications and Equivalence Checking into your FPGA Prototype

Multi-FPGA Prototyping of Over 1.5 Billion ASIC Gates

3:15-3:30 Break


Frontend Implementation

Physical Design

RTL Linting, CDC, DFT & Power


System Integration, Emulation, and FPGA Prototyping


A3 User Session - Optimizing Your Verification Environment

Using Certitude Efficiently

Developing C++ Testbench Components Using UVM Phase and Agent Concepts

B3 User Session - Technical Committee Best Papers from SNUG Europe

Advanced Synthesis Technique Using Target Library Subset

MTCMOS Based Low Power Implementation in GLOBALFOUNDRIES 28nm Process Using UPF2.0 - A Case Study

C3 User & Tutorial Session - ICC II

Investigating the Next Generation Place and Route Tool

Getting Productive in the ICC II GUI

D3 Tutorial Session - Introducing Synopsys SpyGlass

Introduction to Synopsys Spyglass

Introduction to SpyGlass DFT ADV

Introduction to SpyGlass Power

E3 User & Tutorial Session - Efficient Transistor Level implementation

EDA Flow for a Power-Efficient Microprocessor Using iPDK Created from Non-Interoperable oaPDK and Modified Synthesis to Support Asynchronous Logic

Achieving Productive Custom Layout When Using FinFET Devices

F3 User Session - HW Emulation

Enabling Greater Reliability, Scalability, and Flexibility of GPU Emulation with a Hybrid Virtual Machine Based Approach

Multi-Platform Continuum: ZeBu to Post-Silicon ... and Back

5:00-7:00 SNUG Pub and Awards Presentation