SNUG UK 2013 Proceedings

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Complete Proceedings


User Papers and Presentations
A4 - Verification I
Certitude - Achieving Faster Verification Closure Using Design Mutation Analysis (3rd Place - Best Paper)
Author(s): Yogish Sekhar - Dialog Semiconductors
PaperPresentation

A6 - Signoff-Driven Optimisation I
Leakage Power Recovery across Multiple Timing Scenarios
Author(s): Russell Vickers - Intel
PaperPresentation

B1 - FPGA Implementation and FPGA-based Prototyping II
FPGA Prototyping Visibility with Protolink
Author(s): Peter Gibbons - ARM
Presentation

B2 - Low Power Implementation II
IEEE1801 (UPF2.0): Automated and Flexible Approach to Power Management Insertion
Author(s): Conor Byrne - Intel
PaperPresentation

Power Intent Specification: Successful Integration of Hard Macros (Technical Committee Award)
Author(s): Conor Byrne - Intel
PaperPresentation

B3 - High-Performance Implementation II
Achieving Performance Improvements with Design Compiler Block Abstracts
Author(s): Ben Kerr - Broadcom, Martin Phipps - Synopsys Ltd.
Presentation

B4 - Verification II
Going from Custom Methodology to UVM? Do it with a Hybrid.
Author(s): Eric Ohana - ARM Ltd.
PaperPresentation

Making the Most of SystemVerilog and UVM: Hints and Tips for New Users (Technical Committee Award Honorable Mention)
Author(s): David Long - Doulos
PaperPresentation

B6 - Design for Test I
A Hybrid ATPG and Application Testing flow to Localize a Complex RF SoC Failure
Author(s): Kai Wang, Rhys Weaver - CSR Plc., David Johnson - Synopsys Ltd.
PaperPresentation

DFT and ATPG for Mixed 2-phase Latch and Edge Triggered Flop-based Designs
Author(s): Richard Illman - Dialog Semiconductor
PaperPresentation

C1 - FPGA Implementation and FPGA-based Prototyping III
Complex SOC Prototyping using Xilinx Virtex 7 based HAPS-70 Systems (1st Place - Best Paper)
Author(s): Paul Robertson - Broadcom, Andy Jolley - Synopsys Ltd.
PaperPresentation

C2 - Low Power Implementation III
Advanced Retention Power Gating: Unlocking Opportunistic Leakage Savings in High-Performance Mobile SoCs
Author(s): John Biggs, David Flynn, James Myers - ARM
PaperPresentation

Using Formal Equivalence Verification Tool Efficiently on a UPF Design
Author(s): Venkatesh Jakke - Intel
PaperPresentation

C4 - Low Power Verification
Architecting Power Awareness in a Constrained Random OVM Testbench (2nd Place - Best Paper)
Author(s): Kevin Hyland - Intel
PaperPresentation

Low Power Verification using Power State Table Coverage
Author(s): Christophe Lamard, Jean Marie Guillermin - ST Microelectronics, François Cerisier, Mathieu Maisonneuve - Test and Verification Solutions, France
PaperPresentation

Tutorials
A1 - FPGA Implementation and FPGA-based Prototyping I
Effective Implementation of Xilinx 7 Series FPGAs – Methodologies and Techniques for Maximizing Productivity
Author(s): Andy Jolley, Frank McMillan - Synopsys Ltd.
Presentation

A2 - Low Power Implementation I
A Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor
Author(s): Dale Lomelino - Synopsys Inc., Stuart Riches - ARM
Presentation

A3 - High-Performance Implementation I
Achieving Higher Frequencies for Your Design with Early Clock-gating Optimization and Comprehensive Useful Skew
Author(s): Jonathan Dawes - Synopsys Ltd.
Tutorial

Introduction of Multi-Bit Banking Solution
Author(s): Lee Keep - Synopsys Ltd.
Tutorial

A4 - Verification I
VCS Technologies for Best Debug and Analysis
Author(s): Yassine Eben Amine - Synopsys Ltd.
Tutorial

A5 - Analog Mixed-Signal/Full Custom Design I
CCS Noise Characterization Solution
Author(s): Damian Roberts (Synopsys Ltd.)
Tutorial

A6 - Signoff-Driven Optimisation I
PrimeTime 2012.12 Productivity Features: Mode Merging and Leakage Recovery
Author(s): Simon Bloyce - Synopsys Ltd.
Tutorial

B1 - FPGA Implementation and FPGA-based Prototyping II
Introduction to Transaction-Based Verification and Hybrid Prototyping
Author(s): Frank McMillan - Synopsys Ltd.
Tutorial

B5 - Analog Mixed-signal/Full Custom Design II
Advanced Process Node Custom Layout
Author(s): Paul Chapman - Synopsys Ltd.
Tutorial

C1 - FPGA Implementation and FPGA-based Prototyping III
Bring Up and Debug of FPGA Prototypes
Author(s): Mick Posner - Synopsys Ltd.
Tutorial

C3 - High-Performance Implementation III
Engineering Trade-Offs in the Implementation of a High-Performance ARM® Cortex™-A15 Dual Core Processor
Author(s): Joe Walston - Synopsys Inc., Stuart Riches - ARM
Tutorial

C5 - Analog Mixed-signal/Full Custom Design III
Analog and Mixed-signal Verification Methodology Using Verilog-AMS
Author(s): Peter Thompson - Synopsys Inc.
Tutorial

Circuit Simulator Release Update - Getting Ready for the Next Technology Node
Author(s): Dan Zhu - Synopsys Inc.
Tutorial

C6 - Design for Test II
Meeting Quality Goals for Gigascale Designs: Trends and Solutions
Author(s): Dave Johnson - Synopsys Ltd.
Tutorial

Combo
A5 - Analog Mixed-Signal/Full Custom Design I
A Comparison of Dynamic and Static Approaches for the Creation of Liberty Models for Mixed-Signal Macros
Author(s): Oliver King - Moortec Semiconductor, Damian Roberts, Andy Milne - Synopsys Ltd.
Presentation

B3 - High-Performance Implementation II
Deploying a Reference Flow for High-Performance GPU Implementation
Author(s): John Herbert - Imagination Technologies Ltd., Ian Craigen - Synopsys Ltd.
Presentation

B5 - Analog Mixed-signal/Full Custom Design II
Full Custom Layout Automation with Helix
Author(s): Mark Keane - Cambridge Silicon Radio Ltd., Ross Addinall - Synopsys Ltd.
Presentation