SNUG Singapore 2013 Proceedings

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Complete Proceedings

Speeches
Technology Keynote: Advanced Design, Regardless of Process Technology Node
Author(s): Mr. Don Chan, Vice President, Research and Development - Synopsys Inc.

User Papers and Presentations

A Novel Approach of FPGA-Based ATPG Scan Compression
Author(s): Altera Corporation
PaperPresentation

A Realistic Approach To Account LDE Effect In Timing Library Characterization
Author(s): eASIC (M) Sdn Bhd
PaperPresentation

Abstract PCell Schematic
Author(s): eSilicon Corporation, Vietnam
PaperPresentation

An Overview of Quad-Core A7 CPU Implementation
Author(s): MediaTek Singapore
PaperPresentation

Analog Mixed-Signal Simulation in VCS
Author(s): Lite-On Singapore
PaperPresentation

Assistive Split Load Utility for High Fanout Clock Maximum Transition Violations
Author(s): Intel Corporation
PaperPresentation

Automating SoC Based UVM Verification Environments
Author(s): STMicroelectronics Asia Pacific
PaperPresentation

Better ICC to PrimeTime Correlation with Pseudo AOCV Table
Author(s): MediaTek Singapore
PaperPresentation

Cone Extraction Technique for Incremental Static Timing Analysis
Author(s): Intel Corporation
PaperPresentation

Design and Implementation of Custom On-Chip Clock Controller
Author(s): Altera Corporation
PaperPresentation

Design Explorer - The "Little" Design Compiler That Punches Above its Weight
Author(s): Lantiq Asia Pacific
PaperPresentation

DFM Driven Scan Failure Analysis Using Synopsys Yield Explorer
Author(s): GLOBALFOUNDRIES Singapore
PaperPresentation

Optimum Design Planning with DC-Graphical and ICC-DP
Author(s): Altera Corporation
PaperPresentation

Parallel ECO Work Model
Author(s): Intel Corporation
PaperPresentation

Python Based Layout Automation Practice with PyCell Studio
Author(s): GLOBALFOUNDRIES Singapore
PaperPresentation

Sign-Off Accuracy Hierarchical Design Interface Timing Budgeting Flow
Author(s): Altera Corporation
PaperPresentation

Timing Sign-Off Methodology in 20nm Technology: Process and Design Perspective
Author(s): Altera Corporation
PaperPresentation

Publication Only

How We Saved Over a Half Million Dollars in Mask Costs Using the Power of IC Compiler’s Z-route
Author(s): Synopsys, Plano Texas, Texas Instruments Inc.
Publish Only

Improved Fiducial Cells Placement For Optical Probing Efficiency
Author(s): Intel Corporation
Publish Only

Parametric On-chip Variation Analysis
Author(s): PMC
Publish Only

Tutorials

Tutorial: Accelerate Functional ECO Implementation with Formality Ultra
Author(s): Synopsys
Tutorial

Tutorial: AMS Designs in Advance Node
Author(s): Synopsys
Tutorial

Tutorial: An Integrated Approach to Designing the Right SoC Architecture, Starting Software Development and SoC Validation Earlier Using Prototyping
Author(s): Synopsys
Tutorial

Tutorial: Easing Floorplanning with Data Flow Analyzer
Author(s): Synopsys
Tutorial

Tutorial: Galaxy-ECO: The Fastest and Most Effective Solution for DRC, Timing and Leakage Power Closure
Author(s): Synopsys
Tutorial

Tutorial: Pre-route Layer Optimization and Correlation To Post Route
Author(s): Synopsys
Tutorial

Tutorial: Quick FPGA Prototying Platform Bring-up and Design Debug
Author(s): Synopsys
Tutorial

Tutorial: UVM Best Practices
Author(s): Synopsys
Tutorial