SNUG Singapore 2012 Proceedings

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User Papers and Presentations
Enable Advanced Custom Designer Usage Model with P-Cells Creator and SDL Translation (3rd Place - Best Paper - Verification Track)
Author(s): Nam Nguyen, Hieu Vu, Trung Nguyen, Minh Dinh, Nhan Phan (eSilicon Vietnam)
PaperPresentation

A Checklist Approach to Handling Asynchronous Designs
Author(s): Mignon M. Fernandez (BiTMICRO Networks, International Inc.)
Paper

Architecting UVM Based Verification Environments
Author(s): Kiran Bhaskar (STMicroelectronics Asia Pacific Pte Ltd)
PaperPresentation

Automated Interface Timing Constraints Adjustment for Design Convergence
Author(s): Yee Wee Han (Intel Corporation Penang, Malaysia)
PaperPresentation

Automation of Wafer Level Chip-Size Packaging (WLCSP)
Author(s): Bryan D. Alejo (BiTMICRO Networks, International Inc.)
Paper

Building Highly Efficient Hierarchically Tiled Designs in ICC
Author(s): Rob Sanford (Altera Corp)
PaperPresentation

Circuit Check enhancements to reduce false violations for Low Power Design (1st Place - Best Paper - Verification Track)
Author(s): Samaksh Sinha, Ma Fan Yung, Arumugam Saravanan, Luong Nguyen (Infineon Technologies Singapore)
PaperPresentation

Design Compiler Graphical in FPGA Designs (2nd Place - Best Paper - Implementation Track)
Author(s): Gan Chong Gim (Altera)
PaperPresentation

Implementing External Features into a Processor Designer-
Author(s): Bevan A. Pajarillo, Erica May V. Mendoza, Nepomuceno T. Franco II (Bitmicro Networks International, Inc)
PaperPresentation

Improving System Gate-Level Simulation Using VCS New Features (2nd Place - Best Paper - Verification Track)
Author(s): Lawrence M. Salazar (BiTMICRO Networks, International Inc.)
PaperPresentation

Leakage Power Optimization Techniques in High-Speed Design (3rd Place - Best Paper - Implementation Track)
Author(s): Chin Hsiao Chia, Chen Yung Ching (Mediatek Singapore)
PaperPresentation

Managing Test Power Consumption on complex SoC (1st Place - Best Paper - Implementation Track)
Author(s): Shibu Menon, Santhosh Sagar Potharam (ST-Ericcson)
PaperPresentation

Mesh Clock Delay Characterizations With CustomSim-XA
Author(s): Loh Phooi Choong; Ang Boon Chong (Intel Corporation Penang, Malaysia)
Paper

Top 10 STA Tibits!
Author(s): Ang Boon Chong (PMC-Sierra Malaysia)
Paper

Tutorials

Designing Programmable Hardware Accelerators Gaining Flexibility without Compromising Power, Area and Performance
Author(s): Jiff Kuo (Synopsys Taiwan)
Tutorial

Effective Strategies for Bringing Up and Debugging an FPGA-based Prototype
Author(s): Freddy Lin (Synopsys Taiwan)
Tutorial

Faster PrimeTime Signoff –Tips, Tricks & New Technology
Author(s): Jagan Thinakaran (Synopsys Singapore)
Tutorial

Memory Design and Characterization
Author(s): Jiang Xi (Synopsys Singapore)
Tutorial

TCAD Sentaurus
Author(s): Kevin Lin (Synopsys Taiwan)
Tutorial