AI AND MACHINE LEARNING

• Improving productivity and achieving faster QoR closure with machine learning in the Synopsys design flow
• From the data center to the edge – enabling highest performance AI designs with Synopsys implementation solution
• Architecture exploration and early software development with virtual/physical prototyping
• Formal verification of datapath designs
• Using emulation for AI software stack validation
• AI-enabled productivity and performance innovation
• Using virtual test environments for network system validation
• Using AI-ready IP to meet processing, memory, and connectivity requirements for deep learning applications
• The challenges of designing and integrating AI accelerators

AUTOMOTIVE

• Accelerate automotive software development and validation with virtual prototyping
• Complete functional safety verification with industry-leading fault simulation, formal and static verification
• High reliability design techniques for automotive designs
• Hardware security verification
• Implementing safety critical designs for automotive applications
• Designing ISO 26262 required In-System Test using Synopsys tools
• Accelerating ISO 26262 certification with ASIL Ready Certified IP
•  Alpha radiation protection by register cloning, physical separation, and the related physical verification

ANALOG MIXED SIGNAL DESIGN AND SIMULATION

• Addressing analog, custom digital or memory design verification TAT bottlenecks with heterogenous compute acceleration
• RF analysis of RFIC or analog periodic circuits using FineSim
• Ensuring AMS design robustness with advanced variability analysis
• Minimizing design margins with integrated power/signal net electromigration/IR Drop analysis
• Improving AMS design robustness with analog circuit ERC
• Best practices in mixed-signal verification with advanced digital verification methodology with CustomSim and VCS
• How to verify power and signal integrity for multi-gigabit circuits with HSPICE
• Accelerating pre-layout design centering & optimization
• Custom layout productivity gains from using Custom Compiler’s visually assisted automation (symbolic editor, interactive routing, template-based design)
• Mixed custom/digital implementation productivity gains from using Custom Compiler co-design with IC Compiler II or Fusion Compiler
• Faster analog design closure using Custom Compiler early-electrical analysis with StarRC (in-design RC and EM, partial-layout simulation flow)

DESIGN AND VERIFICATION IN THE CLOUD

• Trading off performance vs cost for design or verification in a cloud environment
• Security concerns and best practices in migrating from on-prem to cloud for design and verification
• Allocation and usage of cloud resources for library characterization, simulation, timing analysis and parasitic extraction
• Maximizing available resources with ICV elastic CPU usage
• Impacts on design size partition for physical implementation in a cloud environment
• Leveraging tool runtime scalability in the cloud; what worked best

DIGITAL DESIGN IMPLEMENTATION

• Raising the bar on achieved PPA with Fusion Compiler convergent flow
• Optimal design flow for digital implementation of advanced node designs
• Accelerating time-to-results for large designs with Design Compiler Graphical and IC Compiler II
• Shift-left convergence with RTL Architect by improving constraints and RTL restructuring
• How to achieve best Performance, Power and Area for Arm CPUs
• Using parallel processing to accelerate physical and full chip timing signoff
• Accelerating full chip TAT for large designs using IC Validator physical signoff
• Optimization techniques for low-power IoT designs
• Early time-based peak power analysis with PrimePower with RTL-based vectors
• Using physical-aware ECO capabilities to improve PPA and accelerate timing closure
• Design implementation on the Cloud
• Extending the envelope of Moore’s law with 3D / 2.5D IC design; lessons learned
•  RTL-Level Power Analysis/Estimation
• Concurrent Clock and Data (CCD) Optimizations Techniques
• IR-drop aware STA and related timing fixes. Best practice and automation.

LOW POWER

•  Low-power design for smart edge devices
• AI-driven power considerations
• The quest for energy efficiency: evaluating hardware and software approaches
• Transistor-level vs. system-level energy optimization
• Is Low Low Enough? The Special Power Demands of Crypto Chips

PHYSICAL VERIFICATION CHALLENGES AND SUCCESS

• Getting to fast physical verification at 7nm and below
• Leveraging ICV multi-CPU scalability for fast time-to-results
• Maximizing available resources with ICV elastic CPU usage
• Dirty design handling during SoC integration to minimize runtime and maximize productivity
• Shift-left physical verification analysis and repair utilizing Fusion technology in IC Compiler II and Fusion Compiler

SECURITY

•  Strategies to Reduce Chip Vulnerabilities Through Hardware, IP or Software Approaches
• The Role of an SoC-based Root of Trust for Security
• How to Leverage Standards to Enhance Safety and Security
• Hardware and Software Approaches to Implementing Functional Safety

SIGNOFF

•  How 3DIC design changes signoff
• AI algorithms and their impact on signoff
• Balancing timing, power, power/signal integrity closure

SILICON TEST AND ANALYTICS

• Success with early RTL analysis, physically-aware and area-saving DFT, higher defect detection, lower pattern count/test time, faster and volume diagnostics
• Use of software analytics for accelerating product introduction as well improving yield, test times and quality during high volume production
• Highlighted SoC application areas include AI, automotive, mobile and processors

SUCCESSFUL IP INTEGRATION INTO SoCs

• Interface IP such as 112G Ethernet, Die-to-Die, PCIe 5.0, DDR5/LPDDR5, etc.
• Embedded ARC processors & embedded vision processors
• OTP NVM, embedded memories & logic libraries in advanced FinFET processes
• Integration of IP into high-performance computing, automotive, AI/ML or IoT designs
• Integration of PVT sensor IP monitors and subsystems for enhanced device screening, power and performance optimization, and enhanced resiliency
•  RiscV Embedded Applications

VERIFICATION HARDWARE (INCL. EMULATION, PROTOTYPING)

• Accelerating software bring-up with emulation and prototyping
• Software-driven power analysis for GPUs and AI
• Prototyping with real-world interfaces
• Large complexity prototyping
• Pre-Silicon networking system validation
• SoC performance validation using emulation
• Trust and hardware security verification
• The value of emulation for mission-critical designs
• Insights from power emulation
• Prototyping approaches for 2.5/3D heterogeneous integration
• The insights available from prototyping

VERIFICATION SOFTWARE (INCL. FORMAL VERIFICATION)

• Faster and better convergence using formal methods
• Verification coverage planning and closure
• Best practices for static verification (Lint/CDC/RDC/SDC/LP) signoff
• Accelerating verification and debug for advanced protocols
• Innovations in verification methodology for optimized performance
•  Virtual prototyping applications targeted for Automotive and IoT