TSMC Open Innovation Platform (OIP) Forum

Visit Synopsys at the TSMC Open Innovation Platform (OIP) Forum

Synopsys has a long-standing collaboration with TSMC and a common commitment to provide designers with the best IP, tools, design flows and process technologies.  Stop by the Synopsys booth (#716) to learn more about our design and IP solutions for the most advanced nodes.

Date: September 13, 2017
Hours: 8:30 a.m. to 6:35 p.m.
Location: Santa Clara Convention Center

 

Demo Stations

Learn about the following in the Synopsys Booth #716

  • IC Compiler II – The World Standard for High Performance P&R
  • Silicon-Proven FinFET Design Technology Leadership
  • Custom Design and AMS Verification for FinFETs
  • Silicon-Proven IP for FinFET Processes


See the new Bluetooth solution:

Complete Bluetooth Low Energy Link Layer and PHY IP

This demonstration features Synopsys’ complete DesignWare® Bluetooth Low Energy IP solution operating in two distinct roles – as a central device and a peripheral device. Synopsys’ Bluetooth Low Energy IP solution is compliant with Bluetooth 5 and Bluetooth mesh, and offers a compact, low-power wireless IP solution for IoT applications like wearables, smart home and smart city/industrial.

 

Synopsys at TSMC OIP Ecosystem Forum 2017

EDA Track:

Improving Physical Verification Performance and Productivity for Latest GPU Designs [Joint paper with Nvidia]

Maximizing ROI for 7nm SoCs with Synopsys’ Convergent Digital Design Platform

HiSilicon Achieves PPA Targets Quicker Using PrimeTime POCV to Reduce Design Margin on TSMC N7 FinFET process [Joint paper with HiSilicon]

Stacked Device Enablement for Advanced Analog Design Simulations [Joint paper with Xilinx]

IP Track:

 Foundation IP for High-Performance Computing Designs on TSMC N7 FinFET Process

Accelerating Development of Automotive ADAS SoCs with Certified IP