At Synopsys, we are continuing our rapid pace of innovation and new product rollouts to address the industry’s needs to deliver differentiated solutions to the market faster than ever before. In this session, we will introduce you to a few of these innovations and the value they bring towards achieving our your Power, Performance and Area design goals under today’s challenging conditions.
Shobana Palanisamy, Design Engineer, Arm
Arm will provide insight into the unique challenges of realizing the best power, performance, and area (PPA) targets in the context of a hierarchical design flow, focusing on the newly released Cortex-X1 and upcoming, advanced client processors. Arm will share details of the extensive collaborative work and the resulting flows and methodologies, that mutual customers have already deployed, to realize significant runtime reductions while co-achieving market-shaping performance.
Haroon Gauhar of Arm outlines the design challenges of high-performance cores, where fast RTL feedback and skew optimization are decisive factors of reaching best frequency. He highlights Fusion Compiler’s stable, dependable, and 2X faster throughput, along with CCD everywhere, enabling an efficient production flow that significantly reduced early design margins and improved full-flow PPA.
Dale Lomelino, Sr. Staff Applications Engineer, Synopsys
John Heinlein, Vice President, Chief of Staff to the CEO, Arm
HiSilicon will describe select methodologies and best practices they used to design their mobile AI computing chipset that is deployed in Huawei's flagship smartphones. In this session, you will learn how HiSilicon overcame the challenges in designing a large, complex, highly-integrated SoC on TSMC's 7-nm node with Arm's latest CPU, Cortex®-A76. Their approach leverages Synopsys Fusion Technology for a highly convergent RTL-to-Signoff flow, including physical signoff, that enabled HiSilicon to achieve best PPA and reduce time to tapeout using a massively parallel physical signoff architecture.
f you are designing or planning to design a chip with Arm processors, then attending this session is a must. Using the recently announced Arm® Cortex®-A76 and other current and next generation Arm cores, you will learn from experts best practices and technologies, including machine learning techniques, to efficiently implement Arm's next-generation processors at 7nm and meet challenging performance targets, while minimizing dynamic and leakage power.
Learn how to maximize design QoR and reduce schedules for Arm processor implementation with early accurate power analysis and optimization for power integrity and reliability within IC Compiler™ II, powered by RedHawk™ Analysis Fusion. We will explore how physical designers can leverage this seamless integration and its ease-of-use to enable up to 5x turnaround time improvement vs. point tool power integrity fixing flows, including leveraging self-heat analysis for thermal aware EM checks and RedHawk-SC - big data enabled SoC power integrity and reliability sign-off solution for advanced nodes. Synopsys Fusion Technology™ delivers this tight integration by transparently transferring data between the place-and-route environment and power integrity analysis.