System-Level Catalyst Member


"The coupling of the PLS UDE and Synopsys virtual platforms reduces test times on the real hardware as the joint solution allows more detailed analysis of timing behavior and performance of an embedded application at a very early phase of system design. This prevents downstream errors that cause redesigns and significantly reduces development cost and schedule."

- Heiko Riessland, Product Manager of PLS GmbH 

Product Description

With its innovative modular test and development tools, PLS has demonstrated for almost two decades its position as an international technology leader in the field of debuggers, emulators and trace solutions for 16-bit and 32-bit microcontrollers.

The software architecture of the Universal Debug Engine (UDE) guarantees optimal conditions for debugging SoC-based systems. For example, by means of the intelligent use of modern on-chip debugging and on-chip trace units, valuable functions such as profiling and code coverage are available for the system optimization.

Furthermore, the associated Universal Access Device product family (UAD2/UAD3+) offers entirely new dimensions for fast and flexible access to multi-core systems.

Important architectures such as TriCore, PowerArchitecture, SH 2A, XC2000/XE166, ARM, Cortex, XScale and C166/ST10 as well as simulation platforms are supported. Find out more about PLS products at

Interoperability Description and Customer Benefit

The UDE can establish a connection to Synopsys virtual platforms. The support includes multi-core designs with TriCore, Power Architecture and ARM cores. The solution offers debugging of software at high level language level on the virtual platforms with configuration and control of the processor models. The simple-to-use modular structure of the UDE connection to the Synopsys tools is established via a special target interface component. If the real hardware is available, a simple exchange of this component allows a smooth continuation of work.

Flow Diagram

Flow Diagram